diff --git a/gcc/ChangeLog b/gcc/ChangeLog index dba53343239..16340b695e0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +Wed Feb 13 23:34:30 CET 2002 Jan Hubicka + + * i386.md (mul patterns): Allow memory operand to be first; + add expanders where needed; fix constraints. + (min?f_nonieee, max?f_nonieee, SSE TImode patterns): + Allow memory operand to be the first. + + * i386.c (ix86_prepare_fp_compare_args): Fix condition for swapping + operands. + 2002-02-13 Jakub Jelinek PR c/5681: diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 40f88b5cc2f..e038e5cc7ef 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -7137,7 +7137,7 @@ ix86_prepare_fp_compare_args (code, pop0, pop1) /* Try to rearrange the comparison to make it cheaper. */ if (ix86_fp_comparison_cost (code) > ix86_fp_comparison_cost (swap_condition (code)) - && (GET_CODE (op0) == REG || !reload_completed)) + && (GET_CODE (op1) == REG || !no_new_pseudos)) { rtx tmp; tmp = op0, op0 = op1, op1 = tmp; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index a6e06837377..cdacbbd9019 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -7334,45 +7334,85 @@ (set_attr "prefix_0f" "0,0,1") (set_attr "mode" "HI")]) -(define_insn "mulqi3" +(define_expand "mulqi3" + [(parallel [(set (match_operand:QI 0 "register_operand" "") + (mult:QI (match_operand:QI 1 "nonimmediate_operand" "") + (match_operand:QI 2 "register_operand" ""))) + (clobber (reg:CC 17))])] + "TARGET_QIMODE_MATH" + "") + +(define_insn "*mulqi3_1" [(set (match_operand:QI 0 "register_operand" "=a") - (mult:QI (match_operand:QI 1 "register_operand" "%0") + (mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0") (match_operand:QI 2 "nonimmediate_operand" "qm"))) (clobber (reg:CC 17))] - "TARGET_QIMODE_MATH" + "TARGET_QIMODE_MATH + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{b}\t%2" [(set_attr "type" "imul") (set_attr "length_immediate" "0") (set_attr "mode" "QI")]) -(define_insn "umulqihi3" +(define_expand "umulqihi3" + [(parallel [(set (match_operand:HI 0 "register_operand" "") + (mult:HI (zero_extend:HI + (match_operand:QI 1 "nonimmediate_operand" "")) + (zero_extend:HI + (match_operand:QI 2 "register_operand" "")))) + (clobber (reg:CC 17))])] + "TARGET_QIMODE_MATH" + "") + +(define_insn "*umulqihi3_1" [(set (match_operand:HI 0 "register_operand" "=a") - (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0")) + (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm")))) (clobber (reg:CC 17))] - "TARGET_QIMODE_MATH" + "TARGET_QIMODE_MATH + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{b}\t%2" [(set_attr "type" "imul") (set_attr "length_immediate" "0") (set_attr "mode" "QI")]) -(define_insn "mulqihi3" +(define_expand "mulqihi3" + [(parallel [(set (match_operand:HI 0 "register_operand" "") + (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")) + (sign_extend:HI (match_operand:QI 2 "register_operand" "")))) + (clobber (reg:CC 17))])] + "TARGET_QIMODE_MATH" + "") + +(define_insn "*mulqihi3_insn" [(set (match_operand:HI 0 "register_operand" "=a") - (mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0")) + (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm")))) (clobber (reg:CC 17))] - "TARGET_QIMODE_MATH" + "TARGET_QIMODE_MATH + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{b}\t%2" [(set_attr "type" "imul") (set_attr "length_immediate" "0") (set_attr "mode" "QI")]) -(define_insn "umulditi3" +(define_expand "umulditi3" + [(parallel [(set (match_operand:TI 0 "register_operand" "") + (mult:TI (zero_extend:TI + (match_operand:DI 1 "nonimmediate_operand" "")) + (zero_extend:TI + (match_operand:DI 2 "register_operand" "")))) + (clobber (reg:CC 17))])] + "TARGET_64BIT" + "") + +(define_insn "*umulditi3_insn" [(set (match_operand:TI 0 "register_operand" "=A") - (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "%0")) + (mult:TI (zero_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0")) (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm")))) (clobber (reg:CC 17))] - "TARGET_64BIT" + "TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{q}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") @@ -7380,70 +7420,132 @@ (set_attr "mode" "DI")]) ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers -(define_insn "umulsidi3" +(define_expand "umulsidi3" + [(parallel [(set (match_operand:DI 0 "register_operand" "") + (mult:DI (zero_extend:DI + (match_operand:SI 1 "nonimmediate_operand" "")) + (zero_extend:DI + (match_operand:SI 2 "register_operand" "")))) + (clobber (reg:CC 17))])] + "!TARGET_64BIT" + "") + +(define_insn "*umulsidi3_insn" [(set (match_operand:DI 0 "register_operand" "=A") - (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) + (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0")) (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))) (clobber (reg:CC 17))] - "!TARGET_64BIT" + "!TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{l}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") (set_attr "length_immediate" "0") (set_attr "mode" "SI")]) -(define_insn "mulditi3" +(define_expand "mulditi3" + [(parallel [(set (match_operand:TI 0 "register_operand" "") + (mult:TI (sign_extend:TI + (match_operand:DI 1 "nonimmediate_operand" "")) + (sign_extend:TI + (match_operand:DI 2 "register_operand" "")))) + (clobber (reg:CC 17))])] + "TARGET_64BIT" + "") + +(define_insn "*mulditi3_insn" [(set (match_operand:TI 0 "register_operand" "=A") - (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "%0")) + (mult:TI (sign_extend:TI (match_operand:DI 1 "nonimmediate_operand" "%0")) (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm")))) (clobber (reg:CC 17))] - "TARGET_64BIT" + "TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{q}\t%2" [(set_attr "type" "imul") (set_attr "length_immediate" "0") (set_attr "mode" "DI")]) -(define_insn "mulsidi3" +(define_expand "mulsidi3" + [(parallel [(set (match_operand:DI 0 "register_operand" "") + (mult:DI (sign_extend:DI + (match_operand:SI 1 "nonimmediate_operand" "")) + (sign_extend:DI + (match_operand:SI 2 "register_operand" "")))) + (clobber (reg:CC 17))])] + "!TARGET_64BIT" + "") + +(define_insn "*mulsidi3_insn" [(set (match_operand:DI 0 "register_operand" "=A") - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0")) + (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "%0")) (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm")))) (clobber (reg:CC 17))] - "!TARGET_64BIT" + "!TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{l}\t%2" [(set_attr "type" "imul") (set_attr "length_immediate" "0") (set_attr "mode" "SI")]) +(define_expand "umuldi3_highpart" + [(parallel [(set (match_operand:DI 0 "register_operand" "") + (truncate:DI + (lshiftrt:TI + (mult:TI (zero_extend:TI + (match_operand:DI 1 "nonimmediate_operand" "")) + (zero_extend:TI + (match_operand:DI 2 "register_operand" ""))) + (const_int 64)))) + (clobber (match_scratch:DI 3 "")) + (clobber (reg:CC 17))])] + "TARGET_64BIT" + "") + (define_insn "*umuldi3_highpart_rex64" [(set (match_operand:DI 0 "register_operand" "=d") (truncate:DI (lshiftrt:TI (mult:TI (zero_extend:TI - (match_operand:DI 1 "register_operand" "%a")) + (match_operand:DI 1 "nonimmediate_operand" "%a")) (zero_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))) (const_int 64)))) - (clobber (match_scratch:DI 3 "=a")) + (clobber (match_scratch:DI 3 "=1")) (clobber (reg:CC 17))] - "TARGET_64BIT" + "TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{q}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") (set_attr "length_immediate" "0") (set_attr "mode" "DI")]) -(define_insn "umulsi3_highpart" +(define_expand "umulsi3_highpart" + [(parallel [(set (match_operand:SI 0 "register_operand" "") + (truncate:SI + (lshiftrt:DI + (mult:DI (zero_extend:DI + (match_operand:SI 1 "nonimmediate_operand" "")) + (zero_extend:DI + (match_operand:SI 2 "register_operand" ""))) + (const_int 32)))) + (clobber (match_scratch:SI 3 "")) + (clobber (reg:CC 17))])] + "" + "") + +(define_insn "*umulsi3_highpart_insn" [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI - (match_operand:SI 1 "register_operand" "%a")) + (match_operand:SI 1 "nonimmediate_operand" "%a")) (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) (const_int 32)))) - (clobber (match_scratch:SI 3 "=a")) + (clobber (match_scratch:SI 3 "=1")) (clobber (reg:CC 17))] - "" + "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" "mul{l}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") @@ -7455,48 +7557,78 @@ (zero_extend:DI (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI - (match_operand:SI 1 "register_operand" "%a")) + (match_operand:SI 1 "nonimmediate_operand" "%a")) (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) (const_int 32))))) - (clobber (match_scratch:SI 3 "=a")) + (clobber (match_scratch:SI 3 "=1")) (clobber (reg:CC 17))] - "TARGET_64BIT" + "TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "mul{l}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") (set_attr "length_immediate" "0") (set_attr "mode" "SI")]) +(define_expand "smuldi3_highpart" + [(parallel [(set (match_operand:DI 0 "register_operand" "=d") + (truncate:DI + (lshiftrt:TI + (mult:TI (sign_extend:TI + (match_operand:DI 1 "nonimmediate_operand" "")) + (sign_extend:TI + (match_operand:DI 2 "register_operand" ""))) + (const_int 64)))) + (clobber (match_scratch:DI 3 "")) + (clobber (reg:CC 17))])] + "TARGET_64BIT" + "") + (define_insn "*smuldi3_highpart_rex64" [(set (match_operand:DI 0 "register_operand" "=d") (truncate:DI (lshiftrt:TI (mult:TI (sign_extend:TI - (match_operand:DI 1 "register_operand" "%a")) + (match_operand:DI 1 "nonimmediate_operand" "%a")) (sign_extend:TI (match_operand:DI 2 "nonimmediate_operand" "rm"))) (const_int 64)))) - (clobber (match_scratch:DI 3 "=a")) + (clobber (match_scratch:DI 3 "=1")) (clobber (reg:CC 17))] - "TARGET_64BIT" + "TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{q}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") (set_attr "mode" "DI")]) -(define_insn "smulsi3_highpart" +(define_expand "smulsi3_highpart" + [(parallel [(set (match_operand:SI 0 "register_operand" "") + (truncate:SI + (lshiftrt:DI + (mult:DI (sign_extend:DI + (match_operand:SI 1 "nonimmediate_operand" "")) + (sign_extend:DI + (match_operand:SI 2 "register_operand" ""))) + (const_int 32)))) + (clobber (match_scratch:SI 3 "")) + (clobber (reg:CC 17))])] + "" + "") + +(define_insn "*smulsi3_highpart_insn" [(set (match_operand:SI 0 "register_operand" "=d") (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI - (match_operand:SI 1 "register_operand" "%a")) + (match_operand:SI 1 "nonimmediate_operand" "%a")) (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) (const_int 32)))) - (clobber (match_scratch:SI 3 "=a")) + (clobber (match_scratch:SI 3 "=1")) (clobber (reg:CC 17))] - "" + "GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM" "imul{l}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") @@ -7507,13 +7639,14 @@ (zero_extend:DI (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI - (match_operand:SI 1 "register_operand" "%a")) + (match_operand:SI 1 "nonimmediate_operand" "%a")) (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) (const_int 32))))) - (clobber (match_scratch:SI 3 "=a")) + (clobber (match_scratch:SI 3 "=1")) (clobber (reg:CC 17))] - "TARGET_64BIT" + "TARGET_64BIT + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "imul{l}\t%2" [(set_attr "type" "imul") (set_attr "ppro_uops" "few") @@ -15975,12 +16108,13 @@ (define_insn "*minsf_nonieee" [(set (match_operand:SF 0 "register_operand" "=x#f,f#x") - (if_then_else:SF (lt (match_operand:SF 1 "register_operand" "%0,0") + (if_then_else:SF (lt (match_operand:SF 1 "nonimmediate_operand" "%0,0") (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x")) (match_dup 1) (match_dup 2))) (clobber (reg:CC 17))] - "TARGET_SSE && !TARGET_IEEE_FP" + "TARGET_SSE && !TARGET_IEEE_FP + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "#") (define_split @@ -16057,12 +16191,13 @@ (define_insn "*mindf_nonieee" [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y") - (if_then_else:DF (lt (match_operand:DF 1 "register_operand" "%0,0") + (if_then_else:DF (lt (match_operand:DF 1 "nonimmediate_operand" "%0,0") (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y")) (match_dup 1) (match_dup 2))) (clobber (reg:CC 17))] - "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP" + "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "#") (define_split @@ -16138,12 +16273,13 @@ (define_insn "*maxsf_nonieee" [(set (match_operand:SF 0 "register_operand" "=x#f,f#x") - (if_then_else:SF (gt (match_operand:SF 1 "register_operand" "%0,0") + (if_then_else:SF (gt (match_operand:SF 1 "nonimmediate_operand" "%0,0") (match_operand:SF 2 "nonimmediate_operand" "xm#f,f#x")) (match_dup 1) (match_dup 2))) (clobber (reg:CC 17))] - "TARGET_SSE && !TARGET_IEEE_FP" + "TARGET_SSE && !TARGET_IEEE_FP + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "#") (define_split @@ -16218,12 +16354,13 @@ (define_insn "*maxdf_nonieee" [(set (match_operand:DF 0 "register_operand" "=Y#f,f#Y") - (if_then_else:DF (gt (match_operand:DF 1 "register_operand" "%0,0") + (if_then_else:DF (gt (match_operand:DF 1 "nonimmediate_operand" "%0,0") (match_operand:DF 2 "nonimmediate_operand" "Ym#f,f#Y")) (match_dup 1) (match_dup 2))) (clobber (reg:CC 17))] - "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP" + "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "#") (define_split @@ -18239,17 +18376,19 @@ (define_insn "sse_andti3" [(set (match_operand:TI 0 "register_operand" "=x") - (and:TI (match_operand:TI 1 "register_operand" "%0") + (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE && !TARGET_SSE2" + "TARGET_SSE && !TARGET_SSE2 + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "andps\t{%2, %0|%0, %2}" [(set_attr "type" "sse")]) (define_insn "*sse_andti3_sse2" [(set (match_operand:TI 0 "register_operand" "=x") - (and:TI (match_operand:TI 1 "register_operand" "%0") + (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2" + "TARGET_SSE2 + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "pand\t{%2, %0|%0, %2}" [(set_attr "type" "sse")]) @@ -18319,17 +18458,19 @@ (define_insn "sse_iorti3" [(set (match_operand:TI 0 "register_operand" "=x") - (ior:TI (match_operand:TI 1 "register_operand" "%0") + (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE && !TARGET_SSE2" + "TARGET_SSE && !TARGET_SSE2 + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "orps\t{%2, %0|%0, %2}" [(set_attr "type" "sse")]) (define_insn "*sse_iorti3_sse2" [(set (match_operand:TI 0 "register_operand" "=x") - (ior:TI (match_operand:TI 1 "register_operand" "%0") + (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2" + "TARGET_SSE2 + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "por\t{%2, %0|%0, %2}" [(set_attr "type" "sse")]) @@ -18367,17 +18508,19 @@ (define_insn "sse_xorti3" [(set (match_operand:TI 0 "register_operand" "=x") - (xor:TI (match_operand:TI 1 "register_operand" "%0") + (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE && !TARGET_SSE2" + "TARGET_SSE && !TARGET_SSE2 + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "xorps\t{%2, %0|%0, %2}" [(set_attr "type" "sse")]) (define_insn "*sse_xorti3_sse2" [(set (match_operand:TI 0 "register_operand" "=x") - (xor:TI (match_operand:TI 1 "register_operand" "%0") + (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2" + "TARGET_SSE2 + && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "pxor\t{%2, %0|%0, %2}" [(set_attr "type" "sse")])