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PR target/106122: Don't update %esp via the stack with -Oz on x86. 

When optimizing for size with -Oz, setting a register can be minimized by
pushing an immediate value to the stack and popping it to the destination.
Alas the one general register that shouldn't be updated via the stack is
the stack pointer itself, where "pop %esp" can't be represented in GCC's
RTL ("use of a register mentioned in pre_inc, pre_dec, post_inc or
post_dec is not permitted within the same instruction").  This patch
fixes PR target/106122 by explicitly checking for SP_REG in the
problematic peephole2.

2022-07-O3  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
	PR target/106122
	* config/i386/i386.md (peephole2): Avoid generating pop %esp
	when optimizing for size.

gcc/testsuite/ChangeLog
	PR target/106122
	* gcc.target/i386/pr106122.c: New test case.
This commit is contained in:
Roger Sayle 2022-07-03 14:01:17 +01:00
parent a60152e87c
commit 55899e33de
2 changed files with 17 additions and 1 deletions
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3
gcc/config/i386/i386.md
View File

@ -2519,7 +2519,8 @@
"optimize_insn_for_size_p () && optimize_size > 1
&& operands[1] != const0_rtx
&& IN_RANGE (INTVAL (operands[1]), -128, 127)
&& !ix86_red_zone_used"
&& !ix86_red_zone_used
&& REGNO (operands[0]) != SP_REG"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (match_dup 3))]
{

15
gcc/testsuite/gcc.target/i386/pr106122.c Normal file
View File

@ -0,0 +1,15 @@
/* PR middle-end/106122 */
/* { dg-do compile } */
/* { dg-options "-Oz" } */
register volatile int a __asm__("%esp");
void foo (void *);
void bar (void *);
void
baz (void)
{
foo (__builtin_return_address (0));
a = 0;
bar (__builtin_return_address (0));
}