rs6000: Define define_insn_and_split to split unspec sldi+or to rldimi
Combine pass could recognize the pattern defined and split it in split1, this patch could optimize: 21: r130:DI=r133:DI<<0x20 11: {r129:DI=zero_extend(unspec[[r145:DI]] 87);clobber scratch;} 22: r134:DI=r130:DI|r129:DI to 21: {r149:DI=zero_extend(unspec[[r145:DI]] 87);clobber scratch;} 22: r134:DI=r149:DI&0xffffffff|r133:DI<<0x20 rldimi is generated instead of sldi+or. gcc/ChangeLog: 2020-07-13 Xionghu Luo <luoxhu@linux.ibm.com> * config/rs6000/rs6000.md (rotl_unspec): New define_insn_and_split. gcc/testsuite/ChangeLog: 2020-07-13 Xionghu Luo <luoxhu@linux.ibm.com> * gcc.target/powerpc/vector_float.c: New test.
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@ -4240,6 +4240,32 @@
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operands[5] = GEN_INT ((HOST_WIDE_INT_1U << <bits>) - 1);
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})
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; rldimi with UNSPEC_SI_FROM_SF.
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(define_insn_and_split "*rotldi3_insert_sf"
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[(set (match_operand:DI 0 "gpc_reg_operand")
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(ior:DI
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(ashift:DI (match_operand:DI 1 "gpc_reg_operand")
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(match_operand:SI 2 "const_int_operand"))
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(zero_extend:DI
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(unspec:QHSI
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[(match_operand:SF 3 "memory_operand")]
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UNSPEC_SI_FROM_SF))))
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(clobber (match_scratch:V4SF 4))]
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"INTVAL (operands[2]) == <bits>"
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"#"
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""
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[(parallel [(set (match_dup 5)
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(zero_extend:DI (unspec:QHSI [(match_dup 3)] UNSPEC_SI_FROM_SF)))
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(clobber (match_dup 4))])
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(set (match_dup 0)
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(ior:DI
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(and:DI (match_dup 5) (match_dup 6))
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(ashift:DI (match_dup 1) (match_dup 2))))]
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{
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operands[5] = gen_reg_rtx (DImode);
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operands[6] = GEN_INT ((HOST_WIDE_INT_1U << <bits>) - 1);
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})
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; rlwimi, too.
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(define_split
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[(set (match_operand:SI 0 "gpc_reg_operand")
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15
gcc/testsuite/gcc.target/powerpc/vector_float.c
Normal file
15
gcc/testsuite/gcc.target/powerpc/vector_float.c
Normal file
@ -0,0 +1,15 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target powerpc_p9vector_ok } */
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/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
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vector float
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test (float *a, float *b, float *c, float *d)
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{
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return (vector float){*a, *b, *c, *d};
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}
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/* { dg-final { scan-assembler-not {\mlxssp} } } */
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/* { dg-final { scan-assembler-not {\mlfs} } } */
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/* { dg-final { scan-assembler-times {\mlwz\M} 4 } } */
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/* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */
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/* { dg-final { scan-assembler-times {\mmtvsrdd\M} 1 } } */
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