rs6000: Define define_insn_and_split to split unspec sldi+or to rldimi

Combine pass could recognize the pattern defined and split it in split1,
this patch could optimize:

21: r130:DI=r133:DI<<0x20
11: {r129:DI=zero_extend(unspec[[r145:DI]] 87);clobber scratch;}
22: r134:DI=r130:DI|r129:DI

to

21: {r149:DI=zero_extend(unspec[[r145:DI]] 87);clobber scratch;}
22: r134:DI=r149:DI&0xffffffff|r133:DI<<0x20

rldimi is generated instead of sldi+or.

gcc/ChangeLog:

2020-07-13  Xionghu Luo  <luoxhu@linux.ibm.com>

	* config/rs6000/rs6000.md (rotl_unspec): New
	define_insn_and_split.

gcc/testsuite/ChangeLog:

2020-07-13  Xionghu Luo  <luoxhu@linux.ibm.com>

	* gcc.target/powerpc/vector_float.c: New test.
This commit is contained in:
Xionghu Luo 2020-07-12 20:22:56 -05:00
parent 466dd1629c
commit 56d78c58c2
2 changed files with 41 additions and 0 deletions

View File

@ -4240,6 +4240,32 @@
operands[5] = GEN_INT ((HOST_WIDE_INT_1U << <bits>) - 1);
})
; rldimi with UNSPEC_SI_FROM_SF.
(define_insn_and_split "*rotldi3_insert_sf"
[(set (match_operand:DI 0 "gpc_reg_operand")
(ior:DI
(ashift:DI (match_operand:DI 1 "gpc_reg_operand")
(match_operand:SI 2 "const_int_operand"))
(zero_extend:DI
(unspec:QHSI
[(match_operand:SF 3 "memory_operand")]
UNSPEC_SI_FROM_SF))))
(clobber (match_scratch:V4SF 4))]
"INTVAL (operands[2]) == <bits>"
"#"
""
[(parallel [(set (match_dup 5)
(zero_extend:DI (unspec:QHSI [(match_dup 3)] UNSPEC_SI_FROM_SF)))
(clobber (match_dup 4))])
(set (match_dup 0)
(ior:DI
(and:DI (match_dup 5) (match_dup 6))
(ashift:DI (match_dup 1) (match_dup 2))))]
{
operands[5] = gen_reg_rtx (DImode);
operands[6] = GEN_INT ((HOST_WIDE_INT_1U << <bits>) - 1);
})
; rlwimi, too.
(define_split
[(set (match_operand:SI 0 "gpc_reg_operand")

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@ -0,0 +1,15 @@
/* { dg-do compile } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
vector float
test (float *a, float *b, float *c, float *d)
{
return (vector float){*a, *b, *c, *d};
}
/* { dg-final { scan-assembler-not {\mlxssp} } } */
/* { dg-final { scan-assembler-not {\mlfs} } } */
/* { dg-final { scan-assembler-times {\mlwz\M} 4 } } */
/* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */
/* { dg-final { scan-assembler-times {\mmtvsrdd\M} 1 } } */