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AVX-512. Extend max/min insn patterns.

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gcc/
	* config/i386/sse.md (VI128_256): Delete.
	(define_mode_iterator VI124_256): New.
	(define_mode_iterator VI124_256_AVX512F_AVX512BW): Ditto.
	(define_expand "<code><mode>3<mask_name><round_name>"): Delete.
	(define_expand "<code><VI124_256_AVX512F_AVX512BW:mode>3"): New.
	(define_insn "*avx2_<code><VI124_256:mode>3"): Rename from
	"*avx2_<code><mode>3<mask_name><round_name>" and update mode iterator.
	(define_expand "<code><VI48_AVX512VL:mode>3_mask"): New.
	(define_insn "*avx512bw_<code><VI48_AVX512VL:mode>3<mask_name>"): Ditto.
	(define_insn "<mask_codefor><code><mode>3<mask_name>"): Update mode
	iterator.
	(define_expand "<code><VI8_AVX2:mode>3"): Update pettern generation
	in presence of AVX-512.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215202
This commit is contained in:
Alexander Ivchenko 2014-09-12 07:36:59 +00:00 committed by Kirill Yukhin
parent be746da138
commit 575d952c5d
2 changed files with 106 additions and 53 deletions
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23
gcc/ChangeLog
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@ -1,3 +1,26 @@
2014-09-12 Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>
Ilya Tocar <ilya.tocar@intel.com>
Andrey Turetskiy <andrey.turetskiy@intel.com>
Ilya Verbin <ilya.verbin@intel.com>
Kirill Yukhin <kirill.yukhin@intel.com>
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
* config/i386/sse.md (VI128_256): Delete.
(define_mode_iterator VI124_256): New.
(define_mode_iterator VI124_256_AVX512F_AVX512BW): Ditto.
(define_expand "<code><mode>3<mask_name><round_name>"): Delete.
(define_expand "<code><VI124_256_AVX512F_AVX512BW:mode>3"): New.
(define_insn "*avx2_<code><VI124_256:mode>3"): Rename from
"*avx2_<code><mode>3<mask_name><round_name>" and update mode iterator.
(define_expand "<code><VI48_AVX512VL:mode>3_mask"): New.
(define_insn "*avx512bw_<code><VI48_AVX512VL:mode>3<mask_name>"): Ditto.
(define_insn "<mask_codefor><code><mode>3<mask_name>"): Update mode
iterator.
(define_expand "<code><VI8_AVX2:mode>3"): Update pettern generation
in presence of AVX-512.
2014-09-12 Alexander Ivchenko <alexander.ivchenko@intel.com>
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Anna Tikhonova <anna.tikhonova@intel.com>

136
gcc/config/i386/sse.md
View File

@ -290,9 +290,6 @@
(define_mode_iterator VI8_256_512
[V8DI (V4DI "TARGET_AVX512VL")])
(define_mode_iterator VI128_256
[V4DI V2DI V4SI (V16QI "TARGET_AVX512BW") (V8HI "TARGET_AVX512BW")])
(define_mode_iterator VI1_AVX2
[(V32QI "TARGET_AVX2") V16QI])
@ -499,8 +496,12 @@
(define_mode_iterator VI48_128 [V4SI V2DI])
;; Various 256bit and 512 vector integer mode combinations
(define_mode_iterator VI124_256_48_512
[V32QI V16HI V8SI (V8DI "TARGET_AVX512F") (V16SI "TARGET_AVX512F")])
(define_mode_iterator VI124_256 [V32QI V16HI V8SI])
(define_mode_iterator VI124_256_AVX512F_AVX512BW
[V32QI V16HI V8SI
(V64QI "TARGET_AVX512BW")
(V32HI "TARGET_AVX512BW")
(V16SI "TARGET_AVX512F")])
(define_mode_iterator VI48_256 [V8SI V4DI])
(define_mode_iterator VI48_512 [V16SI V8DI])
(define_mode_iterator VI4_256_8_512 [V8SI V8DI])
@ -9449,71 +9450,100 @@
[(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "<code><mode>3<mask_name><round_name>"
[(set (match_operand:VI124_256_48_512 0 "register_operand")
(maxmin:VI124_256_48_512
(match_operand:VI124_256_48_512 1 "<round_nimm_predicate>")
(match_operand:VI124_256_48_512 2 "<round_nimm_predicate>")))]
"TARGET_AVX2 && <mask_mode512bit_condition> && <round_mode512bit_condition>"
(define_expand "<code><mode>3"
[(set (match_operand:VI124_256_AVX512F_AVX512BW 0 "register_operand")
(maxmin:VI124_256_AVX512F_AVX512BW
(match_operand:VI124_256_AVX512F_AVX512BW 1 "nonimmediate_operand")
(match_operand:VI124_256_AVX512F_AVX512BW 2 "nonimmediate_operand")))]
"TARGET_AVX2"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*avx2_<code><mode>3<mask_name><round_name>"
[(set (match_operand:VI124_256_48_512 0 "register_operand" "=v")
(maxmin:VI124_256_48_512
(match_operand:VI124_256_48_512 1 "<round_nimm_predicate>" "%v")
(match_operand:VI124_256_48_512 2 "<round_nimm_predicate>" "<round_constraint>")))]
"TARGET_AVX2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)
&& <mask_mode512bit_condition> && <round_mode512bit_condition>"
"vp<maxmin_int><ssemodesuffix>\t{<round_mask_op3>%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<round_mask_op3>}"
(define_insn "*avx2_<code><mode>3"
[(set (match_operand:VI124_256 0 "register_operand" "=v")
(maxmin:VI124_256
(match_operand:VI124_256 1 "nonimmediate_operand" "%v")
(match_operand:VI124_256 2 "nonimmediate_operand" "vm")))]
"TARGET_AVX2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "vex")
(set_attr "mode" "OI")])
(define_expand "<code><mode>3_mask"
[(set (match_operand:VI48_AVX512VL 0 "register_operand")
(vec_merge:VI48_AVX512VL
(maxmin:VI48_AVX512VL
(match_operand:VI48_AVX512VL 1 "nonimmediate_operand")
(match_operand:VI48_AVX512VL 2 "nonimmediate_operand"))
(match_operand:VI48_AVX512VL 3 "vector_move_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")))]
"TARGET_AVX512F"
"ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
(define_insn "*avx512bw_<code><mode>3<mask_name>"
[(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
(maxmin:VI48_AVX512VL
(match_operand:VI48_AVX512VL 1 "nonimmediate_operand" "%v")
(match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")))]
"TARGET_AVX512F && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
"vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "OI")])
(set_attr "mode" "<sseinsnmode>")])
(define_insn "<mask_codefor><code><mode>3<mask_name>"
[(set (match_operand:VI128_256 0 "register_operand" "=v")
(maxmin:VI128_256
(match_operand:VI128_256 1 "register_operand" "v")
(match_operand:VI128_256 2 "nonimmediate_operand" "vm")))]
"TARGET_AVX512VL"
[(set (match_operand:VI12_AVX512VL 0 "register_operand" "=v")
(maxmin:VI12_AVX512VL
(match_operand:VI12_AVX512VL 1 "register_operand" "v")
(match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")))]
"TARGET_AVX512BW"
"vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "type" "sseiadd")
(set_attr "prefix" "evex")
(set_attr "mode" "<sseinsnmode>")])
(define_expand "<code><mode>3"
[(set (match_operand:VI8_AVX2 0 "register_operand")
(maxmin:VI8_AVX2
(match_operand:VI8_AVX2 1 "register_operand")
(match_operand:VI8_AVX2 2 "register_operand")))]
[(set (match_operand:VI8_AVX2_AVX512BW 0 "register_operand")
(maxmin:VI8_AVX2_AVX512BW
(match_operand:VI8_AVX2_AVX512BW 1 "register_operand")
(match_operand:VI8_AVX2_AVX512BW 2 "register_operand")))]
"TARGET_SSE4_2"
{
enum rtx_code code;
rtx xops[6];
bool ok;
xops[0] = operands[0];
if (<CODE> == SMAX || <CODE> == UMAX)
if (TARGET_AVX512F
&& (<MODE>mode == V8DImode || TARGET_AVX512VL))
ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);
else
{
xops[1] = operands[1];
xops[2] = operands[2];
enum rtx_code code;
rtx xops[6];
bool ok;
xops[0] = operands[0];
if (<CODE> == SMAX || <CODE> == UMAX)
{
xops[1] = operands[1];
xops[2] = operands[2];
}
else
{
xops[1] = operands[2];
xops[2] = operands[1];
}
code = (<CODE> == UMAX || <CODE> == UMIN) ? GTU : GT;
xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
xops[4] = operands[1];
xops[5] = operands[2];
ok = ix86_expand_int_vcond (xops);
gcc_assert (ok);
DONE;
}
else
{
xops[1] = operands[2];
xops[2] = operands[1];
}
code = (<CODE> == UMAX || <CODE> == UMIN) ? GTU : GT;
xops[3] = gen_rtx_fmt_ee (code, VOIDmode, operands[1], operands[2]);
xops[4] = operands[1];
xops[5] = operands[2];
ok = ix86_expand_int_vcond (xops);
gcc_assert (ok);
DONE;
})
(define_expand "<code><mode>3"