S/390: Mode attrs "bitoff[_plus]" simplify risbg instructions.
Add a new mode attribute to simplify some instruction patterns.
gcc/ChangeLog:
2016-09-23 Dominik Vogt <vogt@linux.vnet.ibm.com>
* config/s390/s390.md (bitoff, bitoff_plus): Neq mode attributes.
("*extzv<mode>_zEC12", "*insv<mode>_zEC12", "*insv<mode>_z10")
("*insv<mode>_zEC12_appendbitsleft")
("*insv<mode>_z10_appendbitsleft", "*r<noxa>sbg_<mode>_sll")
("*r<noxa>sbg_<mode>_srl"): Use new attributes.
gcc/testsuite/ChangeLog:
2016-09-23 Dominik Vogt <vogt@linux.vnet.ibm.com>
* gcc.target/s390/md/rXsbg_mode_sXl.c: Adapt expected assembly
output to the simplified instructions.
From-SVN: r240409
This commit is contained in:
Dominik Vogt
Andreas Krebbel
parent
199d1d488f
commit
576987fc74
@ -1,3 +1,11 @@
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2016-09-23 Dominik Vogt <vogt@linux.vnet.ibm.com>
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* config/s390/s390.md (bitoff, bitoff_plus): Neq mode attributes.
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("*extzv<mode>_zEC12", "*insv<mode>_zEC12", "*insv<mode>_z10")
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("*insv<mode>_zEC12_appendbitsleft")
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("*insv<mode>_z10_appendbitsleft", "*r<noxa>sbg_<mode>_sll")
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("*r<noxa>sbg_<mode>_srl"): Use new attributes.
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2016-09-23 Jakub Jelinek <jakub@redhat.com>
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* ipa-cp.c (ipcp_store_vr_results): Avoid static local
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@ -761,6 +761,9 @@
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;; In place of GET_MODE_BITSIZE (<MODE>mode)
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(define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")])
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;; 64 - bitsize
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(define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")])
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(define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")])
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;; In place of GET_MODE_SIZE (<MODE>mode)
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(define_mode_attr modesize [(DI "8") (SI "4")])
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@ -3754,7 +3757,7 @@
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(match_operand 2 "const_int_operand" "") ; size
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(match_operand 3 "const_int_operand" "")))] ; start]
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"TARGET_ZEC12"
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"risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift
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"risbgn\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift
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[(set_attr "op_type" "RIE")])
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(define_insn "*extzv<mode>_z10"
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@ -3846,7 +3849,7 @@
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(match_operand:GPR 3 "nonimmediate_operand" "d"))]
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"TARGET_ZEC12
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&& (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
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"risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
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"risbgn\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1"
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[(set_attr "op_type" "RIE")])
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(define_insn "*insv<mode>_z10"
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@ -3857,7 +3860,7 @@
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_Z10
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&& (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>"
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"risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1"
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"risbg\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1"
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[(set_attr "op_type" "RIE")
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(set_attr "z10prop" "z10_super_E1")])
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@ -3894,7 +3897,7 @@
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(ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d")
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(match_operand:GPR 4 "nonzero_shift_count_operand" ""))))]
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"TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
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"risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4"
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"risbgn\t%0,%3,<bitoff>,64-%4-1,%4"
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[(set_attr "op_type" "RIE")
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(set_attr "z10prop" "z10_super_E1")])
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@ -3906,7 +3909,7 @@
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(match_operand:GPR 4 "nonzero_shift_count_operand" ""))))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1"
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"risbg\t%0,%3,64-<bitsize>,64-%4-1,%4"
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"risbg\t%0,%3,<bitoff>,64-%4-1,%4"
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[(set_attr "op_type" "RIE")
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(set_attr "z10prop" "z10_super_E1")])
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@ -4035,7 +4038,7 @@
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(match_operand:GPR 3 "nonimmediate_operand" "0")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_Z10"
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"r<noxa>sbg\t%0,%1,64-<bitsize>,63-%2,%2"
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"r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2"
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[(set_attr "op_type" "RIE")])
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;; unsigned {int,long} a, b
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@ -4050,7 +4053,7 @@
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(match_operand:GPR 3 "nonimmediate_operand" "0")))
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(clobber (reg:CC CC_REGNUM))]
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"TARGET_Z10"
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"r<noxa>sbg\t%0,%1,64-<bitsize>+%2,63,64-%2"
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"r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2"
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[(set_attr "op_type" "RIE")])
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;; These two are generated by combine for s.bf &= val.
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@ -1,3 +1,8 @@
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2016-09-23 Dominik Vogt <vogt@linux.vnet.ibm.com>
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* gcc.target/s390/md/rXsbg_mode_sXl.c: Adapt expected assembly
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output to the simplified instructions.
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2016-09-23 Matthew Wahab <matthew.wahab@arm.com>
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* gcc.target/arm/armv8_2_fp16-move-1.c: New.
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@ -39,28 +39,28 @@ rosbg_si_sll (unsigned int a, unsigned int b)
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{
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return a | (b << 1);
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}
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/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-32,63-1,1" 1 } } */
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/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,32,63-1,1" 1 } } */
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__attribute__ ((noinline)) unsigned int
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rosbg_si_srl (unsigned int a, unsigned int b)
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{
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return a | (b >> 2);
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}
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/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-32\\+2,63,64-2" 1 } } */
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/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,32\\+2,63,64-2" 1 } } */
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__attribute__ ((noinline)) unsigned int
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rxsbg_si_sll (unsigned int a, unsigned int b)
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{
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return a ^ (b << 1);
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}
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/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-32,63-1,1" 1 } } */
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/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,32,63-1,1" 1 } } */
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__attribute__ ((noinline)) unsigned int
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rxsbg_si_srl (unsigned int a, unsigned int b)
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{
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return a ^ (b >> 2);
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}
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/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-32\\+2,63,64-2" 1 } } */
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/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,32\\+2,63,64-2" 1 } } */
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__attribute__ ((noinline)) unsigned long long
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di_sll (unsigned long long x)
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@ -79,28 +79,28 @@ rosbg_di_sll (unsigned long long a, unsigned long long b)
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{
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return a | (b << 1);
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}
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/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-64,63-1,1" 1 } } */
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/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,0,63-1,1" 1 } } */
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__attribute__ ((noinline)) unsigned long long
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rosbg_di_srl (unsigned long long a, unsigned long long b)
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{
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return a | (b >> 2);
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}
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/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,64-64\\+2,63,64-2" 1 } } */
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/* { dg-final { scan-assembler-times "rosbg\t%r.,%r.,2,63,64-2" 1 } } */
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__attribute__ ((noinline)) unsigned long long
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rxsbg_di_sll (unsigned long long a, unsigned long long b)
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{
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return a ^ (b << 1);
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}
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/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-64,63-1,1" 1 } } */
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/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,0,63-1,1" 1 } } */
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__attribute__ ((noinline)) unsigned long long
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rxsbg_di_srl (unsigned long long a, unsigned long long b)
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{
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return a ^ (b >> 2);
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}
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/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,64-64\\+2,63,64-2" 1 } } */
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/* { dg-final { scan-assembler-times "rxsbg\t%r.,%r.,2,63,64-2" 1 } } */
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int
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main (void)
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