Add RDRND, F16C and FSGSBASE support to -march=native
Backport from mainline * config/i386/driver-i386.c (host_detect_local_cpu): Support RDRND, F16C and FSGSBASE. From-SVN: r187697
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@ -1,3 +1,11 @@
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2012-05-20 H.J. Lu <hongjiu.lu@intel.com>
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Backport from mainline
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2012-05-20 H.J. Lu <hongjiu.lu@intel.com>
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* config/i386/driver-i386.c (host_detect_local_cpu): Support
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RDRND, F16C and FSGSBASE.
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2012-05-19 Eric Botcazou <ebotcazou@adacore.com>
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Backport from mainline
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@ -397,6 +397,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
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unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
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unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
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unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
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bool arch;
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@ -444,6 +445,8 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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has_aes = ecx & bit_AES;
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has_pclmul = ecx & bit_PCLMUL;
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has_fma = ecx & bit_FMA;
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has_f16c = ecx & bit_F16C;
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has_rdrnd = ecx & bit_RDRND;
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has_cmpxchg8b = edx & bit_CMPXCHG8B;
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has_cmov = edx & bit_CMOV;
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@ -458,6 +461,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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has_bmi = ebx & bit_BMI;
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has_avx2 = ebx & bit_AVX2;
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has_bmi2 = ebx & bit_BMI2;
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has_fsgsbase = ebx & bit_FSGSBASE;
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}
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/* Check cpuid level of extended features. */
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@ -726,10 +730,14 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
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const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
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const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
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const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
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const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
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const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
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options = concat (options, cx16, sahf, movbe, ase, pclmul,
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popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
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tbm, avx, avx2, sse4_2, sse4_1, lzcnt, NULL);
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tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rdrnd,
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f16c, fsgsbase, NULL);
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}
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done:
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