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m68k.md (*clzsi2_cf): Renamed from clzsi2.

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* config/m68k/m68k.md (*clzsi2_cf): Renamed from clzsi2.  Call
CC_STATUS_INIT.
(clzsi2): New expander.
(*clzsi2_68k): New insn.
* config/m68k/m68k.h: Update comment about
CLZ_DEFINED_VALUE_AT_ZERO.

From-SVN: r187731
This commit is contained in:
Andreas Schwab 2012-05-21 18:43:27 +00:00 committed by Andreas Schwab
parent 83e1a7f080
commit 577e03958f
3 changed files with 34 additions and 4 deletions
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9
gcc/ChangeLog
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@ -1,3 +1,12 @@
2012-05-21 Andreas Schwab <schwab@linux-m68k.org>
* config/m68k/m68k.md (*clzsi2_cf): Renamed from clzsi2. Call
CC_STATUS_INIT.
(clzsi2): New expander.
(*clzsi2_68k): New insn.
* config/m68k/m68k.h: Update comment about
CLZ_DEFINED_VALUE_AT_ZERO.
2012-05-21 Aldy Hernandez <aldyh@redhat.com>
* gimple.h (gimple_set_in_transaction): Remove.

4
gcc/config/m68k/m68k.h
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@ -1,6 +1,6 @@
/* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
Free Software Foundation, Inc.
This file is part of GCC.
@ -698,7 +698,7 @@ __transfer_from_trampoline () \
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
/* The ColdFire FF1 instruction returns 32 for zero. */
/* The 68020 BFFFO and ColdFire FF1 instructions return 32 for zero. */
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
#define STORE_FLAG_VALUE (-1)

25
gcc/config/m68k/m68k.md
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@ -4467,12 +4467,33 @@
;; bit indexing instructions
(define_expand "clzsi2"
[(set (match_operand:SI 0 "register_operand" "")
(clz:SI (match_operand:SI 1 "general_operand" "")))]
"ISA_HAS_FF1 || (TARGET_68020 && TARGET_BITFIELD)"
{
if (ISA_HAS_FF1)
operands[1] = force_reg (SImode, operands[1]);
})
(define_insn "*clzsi2_68k"
[(set (match_operand:SI 0 "register_operand" "=d")
(clz:SI (match_operand:SI 1 "general_operand" "do")))]
"TARGET_68020 && TARGET_BITFIELD"
{
CC_STATUS_INIT;
return "bfffo %1{#0:#0},%0";
})
;; ColdFire ff1 instruction implements clz.
(define_insn "clzsi2"
(define_insn "*clzsi2_cf"
[(set (match_operand:SI 0 "register_operand" "=d")
(clz:SI (match_operand:SI 1 "register_operand" "0")))]
"ISA_HAS_FF1"
"ff1 %0"
{
CC_STATUS_INIT;
return "ff1 %0";
}
[(set_attr "type" "ext")])
;; one complement instructions