m68k.md (*clzsi2_cf): Renamed from clzsi2.
* config/m68k/m68k.md (*clzsi2_cf): Renamed from clzsi2. Call CC_STATUS_INIT. (clzsi2): New expander. (*clzsi2_68k): New insn. * config/m68k/m68k.h: Update comment about CLZ_DEFINED_VALUE_AT_ZERO. From-SVN: r187731
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@ -1,3 +1,12 @@
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2012-05-21 Andreas Schwab <schwab@linux-m68k.org>
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* config/m68k/m68k.md (*clzsi2_cf): Renamed from clzsi2. Call
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CC_STATUS_INIT.
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(clzsi2): New expander.
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(*clzsi2_68k): New insn.
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* config/m68k/m68k.h: Update comment about
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CLZ_DEFINED_VALUE_AT_ZERO.
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2012-05-21 Aldy Hernandez <aldyh@redhat.com>
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2012-05-21 Aldy Hernandez <aldyh@redhat.com>
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* gimple.h (gimple_set_in_transaction): Remove.
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* gimple.h (gimple_set_in_transaction): Remove.
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@ -1,6 +1,6 @@
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/* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
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/* Definitions of target machine for GCC for Motorola 680x0/ColdFire.
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Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
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2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
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Free Software Foundation, Inc.
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Free Software Foundation, Inc.
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This file is part of GCC.
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This file is part of GCC.
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@ -698,7 +698,7 @@ __transfer_from_trampoline () \
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#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
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#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
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/* The ColdFire FF1 instruction returns 32 for zero. */
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/* The 68020 BFFFO and ColdFire FF1 instructions return 32 for zero. */
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#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
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#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
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#define STORE_FLAG_VALUE (-1)
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#define STORE_FLAG_VALUE (-1)
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@ -4467,12 +4467,33 @@
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;; bit indexing instructions
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;; bit indexing instructions
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(define_expand "clzsi2"
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[(set (match_operand:SI 0 "register_operand" "")
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(clz:SI (match_operand:SI 1 "general_operand" "")))]
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"ISA_HAS_FF1 || (TARGET_68020 && TARGET_BITFIELD)"
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{
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if (ISA_HAS_FF1)
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operands[1] = force_reg (SImode, operands[1]);
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})
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(define_insn "*clzsi2_68k"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(clz:SI (match_operand:SI 1 "general_operand" "do")))]
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"TARGET_68020 && TARGET_BITFIELD"
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{
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CC_STATUS_INIT;
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return "bfffo %1{#0:#0},%0";
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})
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;; ColdFire ff1 instruction implements clz.
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;; ColdFire ff1 instruction implements clz.
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(define_insn "clzsi2"
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(define_insn "*clzsi2_cf"
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[(set (match_operand:SI 0 "register_operand" "=d")
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[(set (match_operand:SI 0 "register_operand" "=d")
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(clz:SI (match_operand:SI 1 "register_operand" "0")))]
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(clz:SI (match_operand:SI 1 "register_operand" "0")))]
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"ISA_HAS_FF1"
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"ISA_HAS_FF1"
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"ff1 %0"
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{
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CC_STATUS_INIT;
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return "ff1 %0";
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}
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[(set_attr "type" "ext")])
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[(set_attr "type" "ext")])
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;; one complement instructions
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;; one complement instructions
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