From 57d47da6b88574266368ff229863ed694dbd7399 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Sat, 2 Jun 2007 20:29:03 +0200 Subject: [PATCH] revert: sse.md ("sse4_1_blendvpd"): Require "z" class XMM register for operand[3]. Revert: 2007-06-02 Uros Bizjak * config/i386/sse.md ("sse4_1_blendvpd"): Require "z" class XMM register for operand[3]. Adjust asm template. ("sse4_1_blendvpd"): Ditto. ("sse4_1_pblendvb"): Ditto. * config/i386/i386.c (ix86_expand_sse_4_operands_builtin): Do not force operands[3] into xmm0 register for variable blend instructions. From-SVN: r125285 --- gcc/ChangeLog | 7 +----- gcc/config/i386/i386.c | 53 +++++++++++++++++++++++++++-------------- gcc/config/i386/i386.md | 1 + gcc/config/i386/sse.md | 12 +++++----- 4 files changed, 43 insertions(+), 30 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3adf049e8a2..71bbf0d3d93 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,12 +1,7 @@ 2007-06-02 Uros Bizjak - * config/i386/sse.md ("sse4_1_blendvpd"): Require "z" class XMM - register for operand[3]. Adjust asm template. - ("sse4_1_blendvpd"): Ditto. - ("sse4_1_pblendvb"): Ditto. * config/i386/i386.c (ix86_expand_sse_4_operands_builtin): Call - safe_vector_operand() if input operand is VECTOR_MODE_P operand. Do not - force operands[3] into xmm0 register for variable blend instructions. + safe_vector_operand() if input operand is VECTOR_MODE_P operand. (ix86_expand_sse_pcmpestr): Do not check operands for "register_operand", when insn operand predicate is "register_operand". (ix86_expand_sse_pcmpistr): Ditto. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 64fb97ed89f..a150c05dac8 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -18280,14 +18280,13 @@ ix86_expand_sse_4_operands_builtin (enum insn_code icode, tree exp, enum machine_mode tmode = insn_data[icode].operand[0].mode; enum machine_mode mode1 = insn_data[icode].operand[1].mode; enum machine_mode mode2 = insn_data[icode].operand[2].mode; - enum machine_mode mode3 = insn_data[icode].operand[3].mode; + enum machine_mode mode3; + rtx xmm0; if (VECTOR_MODE_P (mode1)) op0 = safe_vector_operand (op0, mode1); if (VECTOR_MODE_P (mode2)) op1 = safe_vector_operand (op1, mode2); - if (VECTOR_MODE_P (mode3)) - op2 = safe_vector_operand (op2, mode3); if (optimize || target == 0 @@ -18301,24 +18300,42 @@ ix86_expand_sse_4_operands_builtin (enum insn_code icode, tree exp, || !(*insn_data[icode].operand[2].predicate) (op1, mode2)) op1 = copy_to_mode_reg (mode2, op1); - if (! (*insn_data[icode].operand[3].predicate) (op2, mode3)) - switch (icode) - { - case CODE_FOR_sse4_1_blendvpd: - case CODE_FOR_sse4_1_blendvps: - case CODE_FOR_sse4_1_pblendvb: + switch (icode) + { + case CODE_FOR_sse4_1_blendvpd: + case CODE_FOR_sse4_1_blendvps: + case CODE_FOR_sse4_1_pblendvb: + mode3 = tmode; + op2 = safe_vector_operand (op2, mode3); + + if (!register_operand (op2, mode3)) op2 = copy_to_mode_reg (mode3, op2); - break; - case CODE_FOR_sse4_1_roundsd: - case CODE_FOR_sse4_1_roundss: - error ("the third argument must be a 4-bit immediate"); - return const0_rtx; + /* ??? The third argument of variable blends must be xmm0. */ + xmm0 = gen_rtx_REG (mode3, XMM0_REG); - default: - error ("the third argument must be an 8-bit immediate"); - return const0_rtx; - } + emit_move_insn (xmm0, op2); + op2 = xmm0; + break; + + default: + mode3 = insn_data[icode].operand[3].mode; + if (! (*insn_data[icode].operand[3].predicate) (op2, mode3)) + { + switch (icode) + { + case CODE_FOR_sse4_1_roundsd: + case CODE_FOR_sse4_1_roundss: + error ("the third argument must be a 4-bit immediate"); + break; + default: + error ("the third argument must be an 8-bit immediate"); + break; + } + return const0_rtx; + } + break; + } pat = GEN_FCN (icode) (target, op0, op1, op2); if (! pat) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 3d101772f05..ad8ad0032f5 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -204,6 +204,7 @@ (FLAGS_REG 17) (FPSR_REG 18) (FPCR_REG 19) + (XMM0_REG 21) (R10_REG 39) (R11_REG 40) ]) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 1f8086f99c7..cd8371771ab 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -5844,10 +5844,10 @@ [(set (match_operand:V2DF 0 "register_operand" "=x") (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0") (match_operand:V2DF 2 "nonimmediate_operand" "xm") - (match_operand:V2DF 3 "register_operand" "z")] + (reg:V2DF XMM0_REG)] UNSPEC_BLENDV))] "TARGET_SSE4_1" - "blendvpd\t{%3, %2, %0|%0, %2, %3}" + "blendvpd\t{%%xmm0, %2, %0|%0, %2, %%xmm0}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "mode" "V2DF")]) @@ -5856,10 +5856,10 @@ [(set (match_operand:V4SF 0 "register_operand" "=x") (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") (match_operand:V4SF 2 "nonimmediate_operand" "xm") - (match_operand:V4SF 3 "register_operand" "z")] + (reg:V4SF XMM0_REG)] UNSPEC_BLENDV))] "TARGET_SSE4_1" - "blendvps\t{%3, %2, %0|%0, %2, %3}" + "blendvps\t{%%xmm0, %2, %0|%0, %2, %%xmm0}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "mode" "V4SF")]) @@ -5927,10 +5927,10 @@ [(set (match_operand:V16QI 0 "register_operand" "=x") (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0") (match_operand:V16QI 2 "nonimmediate_operand" "xm") - (match_operand:V16QI 3 "register_operand" "z")] + (reg:V16QI XMM0_REG)] UNSPEC_BLENDV))] "TARGET_SSE4_1" - "pblendvb\t{%3, %2, %0|%0, %2, %3}" + "pblendvb\t{%%xmm0, %2, %0|%0, %2, %%xmm0}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") (set_attr "mode" "TI")])