m68hc11.md (peephole2): New peephole2 to optimize address computation and memory moves.
* config/m68hc11/m68hc11.md (peephole2): New peephole2 to optimize address computation and memory moves. From-SVN: r55267
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Stephane Carrez
Stephane Carrez
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0d49ec1158
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581fd39277
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@ -1,3 +1,8 @@
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2002-07-06 Stephane Carrez <stcarrez@nerim.fr>
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* config/m68hc11/m68hc11.md (peephole2): New peephole2 to optimize
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address computation and memory moves.
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2002-07-03 Mark Mitchell <mark@codesourcery.com>
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PR c++/6706
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@ -6479,29 +6479,35 @@
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;;--------------------------------------------------------------------
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;;
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;; Reorganize to optimize address computations.
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;; Replace "leas 2,sp" with a "pulx" or a "puly".
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;; On 68HC12, this is one cycle slower but one byte smaller.
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;; pr target/6899: This peephole is not valid because a register CSE
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;; pass removes the pulx/puly.
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;;
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(define_peephole2
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[(set (match_operand:HI 0 "hard_reg_operand" "")
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(match_operand:HI 1 "const_int_operand" ""))
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(set (match_dup 0)
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(plus:HI (match_dup 0)
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(match_operand:HI 2 "general_operand" "")))]
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"(INTVAL (operands[1]) >= -2 && INTVAL (operands[1]) <= 2)"
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[(set (match_dup 0) (match_dup 2))
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(set (match_dup 0) (plus:HI (match_dup 0) (match_dup 1)))]
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"")
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[(set (reg:HI SP_REGNUM) (plus:HI (reg:HI SP_REGNUM) (const_int 2)))
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(match_scratch:HI 0 "xy")]
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"0 && TARGET_M6812 && optimize_size"
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[(set (match_dup 0) (match_dup 1))]
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"operands[1] = gen_rtx (MEM, HImode,
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gen_rtx (POST_INC, HImode,
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gen_rtx_REG (HImode, HARD_SP_REGNUM)));")
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;;
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;; Reorganize address computation based on stack pointer.
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;; Optimize memory<->memory moves when the value is also loaded in
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;; a register.
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;;
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(define_peephole2
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[(set (match_operand:HI 0 "hard_reg_operand" "")
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(match_operand:HI 1 "const_int_operand" ""))
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(set (match_dup 0) (plus:HI (match_dup 0) (reg:HI SP_REGNUM)))]
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""
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[(set (match_dup 0) (reg:HI SP_REGNUM))
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(set (match_dup 0) (plus:HI (match_dup 0) (match_dup 1)))]
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[(set (match_operand:QI 0 "memory_operand" "")
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(match_operand:QI 1 "memory_operand" ""))
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(set (reg:QI D_REGNUM)
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(match_operand:QI 2 "memory_operand" ""))]
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"(rtx_equal_p (operands[0], operands[2]) && !side_effects_p (operands[0]))
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|| (GET_CODE (XEXP (operands[0], 0)) == REG
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&& GET_CODE (XEXP (operands[2], 0)) == POST_INC
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&& rtx_equal_p (XEXP (operands[0], 0), XEXP (XEXP (operands[2], 0), 0)))"
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[(set (reg:QI D_REGNUM) (match_dup 1))
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(set (match_dup 2) (reg:QI D_REGNUM))]
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"")
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;;
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@ -6520,11 +6526,63 @@
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[(set (cc0) (compare (match_dup 1) (match_dup 2)))]
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"")
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;;
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;; Optimize loading a constant to memory when that same constant
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;; is loaded to a hard register. Switch the two to use the register
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;; for memory initialization. In most cases, the constant is 0.
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;;
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(define_peephole2
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[(set (match_operand:HI 0 "memory_operand" "")
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(match_operand:HI 1 "immediate_operand" ""))
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(set (match_operand:HI 2 "hard_reg_operand" "")
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(match_dup 1))]
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"(D_REG_P (operands[2]) || X_REG_P (operands[2]) || Y_REG_P (operands[2]))
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&& !reg_mentioned_p (operands[2], operands[0])
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&& GET_MODE (operands[2]) == HImode"
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[(set (match_dup 2) (match_dup 1))
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(set (match_dup 0) (match_dup 2))]
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"")
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;;
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;; Reorganize to optimize address computations.
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;;
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(define_peephole2
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[(set (match_operand:HI 0 "hard_reg_operand" "")
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(match_operand:HI 1 "const_int_operand" ""))
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(set (match_dup 0)
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(plus:HI (match_dup 0)
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(match_operand:HI 2 "general_operand" "")))]
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"(INTVAL (operands[1]) >= -2 && INTVAL (operands[1]) <= 2)"
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[(set (match_dup 0) (match_dup 2))
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(set (match_dup 0) (plus:HI (match_dup 0) (match_dup 1)))]
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"")
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;;
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;; Optimize an address register increment and a compare to use
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;; a PRE_INC or PRE_DEC addressing mode (disabled on the compare insn
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;; a PRE_INC or PRE_DEC addressing mode (disabled on the tst insn
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;; before reload, but can be enabled after).
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;;
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(define_peephole2
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[(set (match_operand:HI 0 "hard_reg_operand" "")
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(plus:HI (match_dup 0)
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(match_operand:HI 1 "const_int_operand" "")))
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(set (cc0)
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(match_operand:QI 2 "memory_operand" ""))]
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"TARGET_AUTO_INC_DEC
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&& (INTVAL (operands[1]) == -1 || INTVAL (operands[1]) == 1)
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&& reg_mentioned_p (operands[0], operands[2])"
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[(set (cc0) (match_dup 3))]
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"if (INTVAL (operands[1]) == 1)
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operands[3] = gen_rtx (MEM, QImode,
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gen_rtx (PRE_INC, HImode, operands[0]));
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else
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operands[3] = gen_rtx (MEM, QImode,
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gen_rtx (PRE_DEC, HImode, operands[0]));
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")
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;;
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;; Likewise for compare.
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;;
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(define_peephole2
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[(set (match_operand:HI 0 "hard_reg_operand" "")
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(plus:HI (match_dup 0)
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@ -6563,6 +6621,47 @@
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gen_rtx (PRE_DEC, HImode, operands[0]));
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")
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;;
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;; Replace a "ldx #N; addx <sp>" with a "ldx <sp>; addx #n"
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;; (avoids many temporary moves because we can't add sp to another reg easily)
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;;
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(define_peephole2
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[(set (match_operand:HI 0 "hard_reg_operand" "")
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(match_operand:HI 1 "const_int_operand" ""))
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(set (match_dup 0) (plus:HI (match_dup 0) (reg:HI SP_REGNUM)))]
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""
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[(set (match_dup 0) (reg:HI SP_REGNUM))
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(set (match_dup 0) (plus:HI (match_dup 0) (match_dup 1)))]
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"")
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;;
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;; Replace "ldd #N; addd <op>" with "ldd <op>; addd #N".
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;;
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(define_peephole2
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[(set (match_operand:HI 0 "hard_reg_operand" "")
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(match_operand:HI 1 "const_int_operand" ""))
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(set (match_dup 0)
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(plus:HI (match_dup 0)
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(match_operand:HI 2 "general_operand" "")))]
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"(INTVAL (operands[1]) >= -2 && INTVAL (operands[1]) <= 2)"
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[(set (match_dup 0) (match_dup 2))
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(set (match_dup 0) (plus:HI (match_dup 0) (match_dup 1)))]
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"")
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;;
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;; Replace a "ldd <mem>; psha; pshb" with a "ldx <mem>; pshx".
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;;
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(define_peephole2
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[(set (match_operand:HI 0 "hard_reg_operand" "")
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(match_operand:HI 1 "memory_operand" ""))
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(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM)))
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(match_dup 0))
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(match_scratch:HI 2 "x")]
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"TARGET_M6811 && D_REG_P (operands[0]) && peep2_reg_dead_p (2, operands[0])"
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[(set (match_dup 2) (match_dup 1))
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(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 2))]
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"")
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;;
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;; This peephole catches the address computations generated by the reload
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;; pass.
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