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[MIPS] Scheduler fix for the 74k & 24k. 

2015-08-12  Simon Dardis  <simon.dardis@imgtec.com>

gcc/
	* config/mips/mips.c (mips_store_data_bypass_p): Bring code into
	line with comments.
	* config/mips/sb1.md: Update usage of mips_store_data_bypass_p.

From-SVN: r226805
This commit is contained in:
Simon Dardis 2015-08-12 11:44:56 +01:00 committed by Robert Suchanek
parent bde351d539
commit 585d372b05
3 changed files with 10 additions and 4 deletions
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6
gcc/ChangeLog
View File

@ -1,3 +1,9 @@
2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
* config/mips/mips.c (mips_store_data_bypass_p): Bring code into
line with comments.
* config/mips/sb1.md: Update usage of mips_store_data_bypass_p.
2015-08-12 Richard Biener <rguenther@suse.de>
* gimple.h (remove_pointer): New trait.

2
gcc/config/mips/mips.c
View File

@ -13615,7 +13615,7 @@ mips_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
if (GET_CODE (PATTERN (in_insn)) == UNSPEC_VOLATILE)
return false;
return !store_data_bypass_p (out_insn, in_insn);
return store_data_bypass_p (out_insn, in_insn);
}

6
gcc/config/mips/sb1.md
View File

@ -216,7 +216,7 @@
"ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp,
ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp"
"ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
"mips_store_data_bypass_p")
"!mips_store_data_bypass_p")
;; On SB-1, simple alu instructions can execute on the LS1 unit.
@ -289,7 +289,7 @@
(define_bypass 5
"ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo"
"ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
"mips_store_data_bypass_p")
"!mips_store_data_bypass_p")
;; mf{hi,lo} is 1 cycle.
@ -351,7 +351,7 @@
(define_bypass 7
"ir_sb1_mulsi,ir_sb1_muldi"
"ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore"
"mips_store_data_bypass_p")
"!mips_store_data_bypass_p")
;; The divide unit is not pipelined. Divide busy is asserted in the 4th
;; cycle, and then deasserted on the latency cycle. So only one divide at