* doc/invoke.texi: Update Alpha options.
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2002-01-12 Richard Henderson <rth@redhat.com>
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* doc/invoke.texi: Update Alpha options.
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* doc/invoke.texi: Update i386 built-in function lists.
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Sat Jan 12 17:38:11 CET 2002 Jan Hubicka <jh@suse.cz>
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@ -514,13 +514,14 @@ in the following sections.
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@emph{DEC Alpha Options}
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@gccoptlist{
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-mfp-regs -mno-fp-regs -mno-soft-float -msoft-float @gol
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-malpha-as -mgas @gol
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-mno-fp-regs -msoft-float -malpha-as -mgas @gol
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-mieee -mieee-with-inexact -mieee-conformant @gol
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-mfp-trap-mode=@var{mode} -mfp-rounding-mode=@var{mode} @gol
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-mtrap-precision=@var{mode} -mbuild-constants @gol
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-mcpu=@var{cpu-type} @gol
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-mbwx -mno-bwx -mcix -mno-cix -mmax -mno-max @gol
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-mcpu=@var{cpu-type} -mtune=@var{cpu-type} @gol
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-mbwx -mmax -mfix -mcix @gol
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-mfloat-vax -mfloat-ieee @gol
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-mexplicit-relocs -msmall-data -mlarge-data @gol
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-mmemory-latency=@var{time}}
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@emph{DEC Alpha/VMS Options}
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@ -8275,8 +8276,8 @@ Generate code that uses (does not use) the floating-point register set.
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@option{-mno-fp-regs} implies @option{-msoft-float}. If the floating-point
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register set is not used, floating point operands are passed in integer
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registers as if they were integers and floating-point results are passed
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in $0 instead of $f0. This is a non-standard calling sequence, so any
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function with a floating-point argument or return value called by code
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in @code{$0} instead of @code{$f0}. This is a non-standard calling sequence,
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so any function with a floating-point argument or return value called by code
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compiled with @option{-mno-fp-regs} must also be compiled with that
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option.
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@ -8419,33 +8420,77 @@ assembler (@option{-malpha-as}) or by the GNU assembler @option{-mgas}.
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@itemx -mno-bwx
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@itemx -mcix
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@itemx -mno-cix
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@itemx -mfix
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@itemx -mno-fix
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@itemx -mmax
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@itemx -mno-max
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@opindex mbwx
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@opindex mno-bwx
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@opindex mcix
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@opindex mno-cix
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@opindex mfix
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@opindex mno-fix
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@opindex mmax
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@opindex mno-max
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Indicate whether GCC should generate code to use the optional BWX,
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CIX, and MAX instruction sets. The default is to use the instruction sets
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supported by the CPU type specified via @option{-mcpu=} option or that
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CIX, FIX and MAX instruction sets. The default is to use the instruction
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sets supported by the CPU type specified via @option{-mcpu=} option or that
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of the CPU on which GCC was built if none was specified.
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@item -mfloat-vax
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@itemx -mfloat-ieee
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@opindex mfloat-vax
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@opindex mfloat-ieee
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Generate code that uses (does not use) VAX F and G floating point
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arithmetic instead of IEEE single and double precision.
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@item -mexplicit-relocs
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@itemx -mno-explicit-relocs
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@opindex mexplicit-relocs
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@opindex mno-explicit-relocs
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Older Alpha assemblers provided no way to generate symbol relocations
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except via assembler macros. Use of these macros does not allow
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optimial instruction scheduling. GNU binutils as of version 2.12
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supports a new syntax that allows the compiler to explicitly mark
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which relocations should apply to which instructions. This option
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is mostly useful for debugging, as GCC detects the capabilities of
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the assembler when it is built and sets the default accordingly.
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@item -msmall-data
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@itemx -mlarge-data
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@opindex msmall-data
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@opindex mlarge-data
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When @option{-mexplicit-relocs} is in effect, static data is
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accessed via @dfn{gp-relative} relocations. When @option{-msmall-data}
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is used, objects 8 bytes long or smaller are placed in a @dfn{small data area}
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(the @code{.sdata} and @code{.sbss} sections) and are accessed via
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16-bit relocations off of the @code{$gp} register. This limits the
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size of the small data area to 64KB, but allows the variables to be
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directly accessed via a single instruction.
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The default is @option{-mlarge-data}. With this option the data area
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is limited to just below 2GB. Programs that require more than 2GB of
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data must use @code{malloc} or @code{mmap} to allocate the data in the
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heap instead of in the program's data segment.
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When generating code for shared libraries, @option{-fpic} implies
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@option{-msmall-data} and @option{-fPIC} implies @option{-mlarge-data}.
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@item -mcpu=@var{cpu_type}
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@opindex mcpu
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Set the instruction set, register set, and instruction scheduling
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parameters for machine type @var{cpu_type}. You can specify either the
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@samp{EV} style name or the corresponding chip number. GCC
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supports scheduling parameters for the EV4 and EV5 family of processors
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and will choose the default values for the instruction set from
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the processor you specify. If you do not specify a processor type,
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GCC will default to the processor on which the compiler was built.
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Set the instruction set and instruction scheduling parameters for
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machine type @var{cpu_type}. You can specify either the @samp{EV}
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style name or the corresponding chip number. GCC supports scheduling
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parameters for the EV4, EV5 and EV6 family of processors and will
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choose the default values for the instruction set from the processor
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you specify. If you do not specify a processor type, GCC will default
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to the processor on which the compiler was built.
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Supported values for @var{cpu_type} are
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@table @samp
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@item ev4
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@item ev45
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@itemx 21064
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Schedules as an EV4 and has no instruction set extensions.
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@ -8464,10 +8509,18 @@ Schedules as an EV5 and supports the BWX and MAX extensions.
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@item ev6
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@itemx 21264
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Schedules as an EV5 (until Digital releases the scheduling parameters
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for the EV6) and supports the BWX, CIX, and MAX extensions.
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Schedules as an EV6 and supports the BWX, FIX, and MAX extensions.
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@item ev67
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@item 21264a
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Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions.
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@end table
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@item -mtune=@var{cpu_type}
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@opindex mtune
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Set only the instruction scheduling parameters for machine type
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@var{cpu_type}. The instruction set is not changed.
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@item -mmemory-latency=@var{time}
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@opindex mmemory-latency
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Sets the latency the scheduler should assume for typical memory
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