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sh.c (calc_live_regs): Save FPSCR_REG in an interrupt handler if it is ever live. 

* sh.c (calc_live_regs): Save FPSCR_REG in an interrupt handler
	if it is ever live.

	* sh.c (sh_handle_interrupt_handler_attribute): Reject interrupt_handler
	attribute for SHCOMPACT.

	* sh.h (OVERRIDE_OPTIONS): If align_function isn't set, set it
	appropriately.
	(FUNCTION_BOUNDARY): Specify only the minimum alignment required
	by the ABI.

	* sh.h (SH5_WOULD_BE_PARTIAL_NREGS): Also handle TImode case.

From-SVN: r56637
This commit is contained in:
J"orn Rennecke 2002-08-28 17:37:54 +00:00 committed by Joern Rennecke
parent 6625f89451
commit 58ab7171be
3 changed files with 33 additions and 7 deletions
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15
gcc/ChangeLog
View File

@ -1,3 +1,18 @@
Wed Aug 28 15:35:17 2002 J"orn Rennecke <joern.rennecke@superh.com>
* sh.c (calc_live_regs): Save FPSCR_REG in an interrupt handler
if it is ever live.
* sh.c (sh_handle_interrupt_handler_attribute): Reject interrupt_handler
attribute for SHCOMPACT.
* sh.h (OVERRIDE_OPTIONS): If align_function isn't set, set it
appropriately.
(FUNCTION_BOUNDARY): Specify only the minimum alignment required
by the ABI.
* sh.h (SH5_WOULD_BE_PARTIAL_NREGS): Also handle TImode case.
2002-08-28 Jason Thorpe <thorpej@wasabisystems.com>
* config.gcc (mips*-*-netbsd*): Set target_cpu_default to

7
gcc/config/sh/sh.c
View File

@ -4440,7 +4440,7 @@ calc_live_regs (count_ptr, live_regs_mask)
&& pr_live))
&& reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
&& reg != RETURN_ADDRESS_POINTER_REGNUM
&& reg != T_REG && reg != GBR_REG && reg != FPSCR_REG)
&& reg != T_REG && reg != GBR_REG)
: (/* Only push those regs which are used and need to be saved. */
regs_ever_live[reg] && ! call_used_regs[reg]))
{
@ -5677,6 +5677,11 @@ sh_handle_interrupt_handler_attribute (node, name, args, flags, no_add_attrs)
IDENTIFIER_POINTER (name));
*no_add_attrs = true;
}
else if (TARGET_SHCOMPACT)
{
error ("attribute interrupt_handler is not compatible with -m5-compact");
*no_add_attrs = true;
}
return NULL_TREE;
}

18
gcc/config/sh/sh.h
View File

@ -472,6 +472,14 @@ do { \
break global alloc, and generates slower code anyway due \
to the pressure on R0. */ \
flag_schedule_insns = 0; \
\
/* Allocation boundary (in *bits*) for the code of a function. \
SH1: 32 bit alignment is faster, because instructions are always \
fetched as a pair from a longword boundary. \
SH2 .. SH5 : align to cache line start. */ \
if (align_functions == 0) \
align_functions \
= TARGET_SMALLCODE ? FUNCTION_BOUNDARY : (1 << CACHE_LOG) * 8; \
} while (0)
/* Target machine storage layout. */
@ -532,11 +540,9 @@ do { \
The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
#define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
/* Allocation boundary (in *bits*) for the code of a function.
32 bit alignment is faster, because instructions are always fetched as a
pair from a longword boundary. */
#define FUNCTION_BOUNDARY \
(TARGET_SMALLCODE ? 16 << TARGET_SHMEDIA : (1 << CACHE_LOG) * 8)
/* ABI given & required minimum allocation boundary (in *bits*) for the
code of a function. */
#define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
/* On SH5, the lowest bit is used to indicate SHmedia functions, so
the vbit must go into the delta field of
@ -2018,7 +2024,7 @@ struct sh_args {
: 0)
#define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
(TARGET_SH5 && (MODE) == BLKmode \
(TARGET_SH5 && ((MODE) == BLKmode || (MODE) == TImode) \
&& ((CUM).arg_count[(int) SH_ARG_INT] \
+ (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))