From 58ee9e663594196b2b76669df15e12c1aeff53bf Mon Sep 17 00:00:00 2001 From: Segher Boessenkool Date: Fri, 23 May 2014 18:37:55 +0200 Subject: [PATCH] rs6000: Make all insert instructions one type This uses the attribute "size" to specify the differences: insert_word -> insert size=32 insert_dword -> insert size=64 It could use "dot" as well, but the current code doesn't handle that. From-SVN: r210868 --- gcc/ChangeLog | 36 +++++++++++++++++++++++++++++++++++ gcc/config/rs6000/40x.md | 2 +- gcc/config/rs6000/440.md | 2 +- gcc/config/rs6000/476.md | 2 +- gcc/config/rs6000/601.md | 2 +- gcc/config/rs6000/603.md | 2 +- gcc/config/rs6000/6xx.md | 2 +- gcc/config/rs6000/7450.md | 2 +- gcc/config/rs6000/7xx.md | 2 +- gcc/config/rs6000/8540.md | 2 +- gcc/config/rs6000/cell.md | 9 ++++++--- gcc/config/rs6000/e300c2c3.md | 2 +- gcc/config/rs6000/e500mc.md | 2 +- gcc/config/rs6000/e500mc64.md | 2 +- gcc/config/rs6000/e5500.md | 2 +- gcc/config/rs6000/e6500.md | 2 +- gcc/config/rs6000/mpc.md | 2 +- gcc/config/rs6000/power4.md | 9 ++++++--- gcc/config/rs6000/power5.md | 9 ++++++--- gcc/config/rs6000/power6.md | 6 ++++-- gcc/config/rs6000/power7.md | 2 +- gcc/config/rs6000/power8.md | 2 +- gcc/config/rs6000/rs6000.c | 12 +++++------- gcc/config/rs6000/rs6000.md | 21 ++++++++++---------- gcc/config/rs6000/rs64.md | 2 +- gcc/config/rs6000/titan.md | 2 +- 26 files changed, 93 insertions(+), 47 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 89c4f21431a..b0a478a27b3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,39 @@ +2014-05-23 Segher Boessenkool + + * config/rs6000/rs6000.md (type): Delete "insert_word", + "insert_dword". Add "insert". + (size): Update comment. + * config/rs6000/rs6000.c (rs6000_adjust_cost, is_cracked_insn, + insn_must_be_first_in_group): Adjust. + (insvsi_internal, *insvsi_internal1, *insvsi_internal2, + *insvsi_internal3, *insvsi_internal4, *insvsi_internal5, + *insvsi_internal6, insvdi_internal): Adjust. + + * config/rs6000/40x.md (ppc403-integer): Adjust. + * config/rs6000/440.md (ppc440-integer): Adjust. + * config/rs6000/476.md (ppc476-simple-integer): Adjust. + * config/rs6000/601.md (ppc601-integer): Adjust. + * config/rs6000/603.md (ppc603-integer): Adjust. + * config/rs6000/6xx.md (ppc604-integer): Adjust. + * config/rs6000/7450.md (ppc7450-integer): Adjust. + * config/rs6000/7xx.md (ppc750-integer): Adjust. + * config/rs6000/8540.md (ppc8540_su): Adjust. + * config/rs6000/cell.md (cell-integer, cell-insert): Adjust. + * config/rs6000/e300c2c3.md (ppce300c3_iu): Adjust. + * config/rs6000/e500mc.md (e500mc_su): Adjust. + * config/rs6000/e500mc64.md (e500mc64_su): Adjust. + * config/rs6000/e5500.md (e5500_sfx): Adjust. + * config/rs6000/e6500.md (e6500_sfx): Adjust. + * config/rs6000/mpc.md (mpccore-integer): Adjust. + * config/rs6000/power4.md (power4-integer, power4-insert): Adjust. + * config/rs6000/power5.md (power5-integer, power5-insert): Adjust. + * config/rs6000/power6.md (power6-insert, power6-insert-dword): + Adjust. + * config/rs6000/power7.md (power7-integer): Adjust. + * config/rs6000/power8.md (power8-1cyc): Adjust. + * config/rs6000/rs64.md (rs64a-integer): Adjust. + * config/rs6000/titan.md (titan_fxu_shift_and_rotate): Adjust. + 2014-05-23 Segher Boessenkool * config/rs6000/rs6000.md (type): Add "mul". Delete "imul", diff --git a/gcc/config/rs6000/40x.md b/gcc/config/rs6000/40x.md index 7ec28011446..02971cbeef4 100644 --- a/gcc/config/rs6000/40x.md +++ b/gcc/config/rs6000/40x.md @@ -36,7 +36,7 @@ "iu_40x") (define_insn_reservation "ppc403-integer" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ + (and (eq_attr "type" "integer,insert,shift,trap,\ var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc403,ppc405")) "iu_40x") diff --git a/gcc/config/rs6000/440.md b/gcc/config/rs6000/440.md index 55d115580bf..292177d5e14 100644 --- a/gcc/config/rs6000/440.md +++ b/gcc/config/rs6000/440.md @@ -53,7 +53,7 @@ "ppc440_issue,ppc440_l_pipe") (define_insn_reservation "ppc440-integer" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\ + (and (eq_attr "type" "integer,insert,shift,\ trap,var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc440")) "ppc440_issue,ppc440_i_pipe|ppc440_j_pipe") diff --git a/gcc/config/rs6000/476.md b/gcc/config/rs6000/476.md index 7b006321650..403752a9d62 100644 --- a/gcc/config/rs6000/476.md +++ b/gcc/config/rs6000/476.md @@ -63,7 +63,7 @@ ppc476_lj_pipe") (define_insn_reservation "ppc476-simple-integer" 1 - (and (eq_attr "type" "integer,insert_word,var_shift_rotate,exts,shift") + (and (eq_attr "type" "integer,insert,var_shift_rotate,exts,shift") (eq_attr "cpu" "ppc476")) "ppc476_issue,\ ppc476_i_pipe|ppc476_lj_pipe") diff --git a/gcc/config/rs6000/601.md b/gcc/config/rs6000/601.md index c1a00438859..d0afcf710ac 100644 --- a/gcc/config/rs6000/601.md +++ b/gcc/config/rs6000/601.md @@ -45,7 +45,7 @@ "iu_ppc601+fpu_ppc601") (define_insn_reservation "ppc601-integer" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\ + (and (eq_attr "type" "integer,insert,shift,\ trap,var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc601")) "iu_ppc601") diff --git a/gcc/config/rs6000/603.md b/gcc/config/rs6000/603.md index 7e411264fd5..e6cc444362b 100644 --- a/gcc/config/rs6000/603.md +++ b/gcc/config/rs6000/603.md @@ -58,7 +58,7 @@ "lsu_603") (define_insn_reservation "ppc603-integer" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ + (and (eq_attr "type" "integer,insert,shift,trap,\ var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc603")) "iu_603") diff --git a/gcc/config/rs6000/6xx.md b/gcc/config/rs6000/6xx.md index 429e8628fc6..3a3271e6eff 100644 --- a/gcc/config/rs6000/6xx.md +++ b/gcc/config/rs6000/6xx.md @@ -73,7 +73,7 @@ "lsu_6xx") (define_insn_reservation "ppc604-integer" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ + (and (eq_attr "type" "integer,insert,shift,trap,\ var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) "iu1_6xx|iu2_6xx") diff --git a/gcc/config/rs6000/7450.md b/gcc/config/rs6000/7450.md index b7b5efd0898..a6a4a1b1b49 100644 --- a/gcc/config/rs6000/7450.md +++ b/gcc/config/rs6000/7450.md @@ -73,7 +73,7 @@ "ppc7450_du,lsu_7450") (define_insn_reservation "ppc7450-integer" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\ + (and (eq_attr "type" "integer,insert,shift,\ trap,var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc7450")) "ppc7450_du,iu1_7450|iu2_7450|iu3_7450") diff --git a/gcc/config/rs6000/7xx.md b/gcc/config/rs6000/7xx.md index 059d006f254..332a663f360 100644 --- a/gcc/config/rs6000/7xx.md +++ b/gcc/config/rs6000/7xx.md @@ -61,7 +61,7 @@ "ppc750_du,lsu_7xx") (define_insn_reservation "ppc750-integer" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\ + (and (eq_attr "type" "integer,insert,shift,\ trap,var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc750,ppc7400")) "ppc750_du,iu1_7xx|iu2_7xx") diff --git a/gcc/config/rs6000/8540.md b/gcc/config/rs6000/8540.md index da3f92b0a23..53545eeb71c 100644 --- a/gcc/config/rs6000/8540.md +++ b/gcc/config/rs6000/8540.md @@ -84,7 +84,7 @@ ;; Simple SU insns (define_insn_reservation "ppc8540_su" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\ + (and (eq_attr "type" "integer,insert,cmp,compare,\ delayed_compare,var_delayed_compare,fast_compare,\ shift,trap,var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppc8540,ppc8548")) diff --git a/gcc/config/rs6000/cell.md b/gcc/config/rs6000/cell.md index 8c3c7413da3..3a2668f211e 100644 --- a/gcc/config/rs6000/cell.md +++ b/gcc/config/rs6000/cell.md @@ -166,8 +166,10 @@ ;; Integer latency is 2 cycles (define_insn_reservation "cell-integer" 2 - (and (eq_attr "type" "integer,insert_dword,shift,trap,\ - var_shift_rotate,cntlz,exts,isel") + (and (ior (eq_attr "type" "integer,shift,trap,\ + var_shift_rotate,cntlz,exts,isel") + (and (eq_attr "type" "insert") + (eq_attr "size" "64"))) (eq_attr "cpu" "cell")) "slot01,fxu_cell") @@ -185,7 +187,8 @@ ;; rlwimi, alter cr0 (define_insn_reservation "cell-insert" 2 - (and (eq_attr "type" "insert_word") + (and (eq_attr "type" "insert") + (eq_attr "size" "32") (eq_attr "cpu" "cell")) "slot01,fxu_cell") diff --git a/gcc/config/rs6000/e300c2c3.md b/gcc/config/rs6000/e300c2c3.md index aba0d206e7c..e9c8f18a0c7 100644 --- a/gcc/config/rs6000/e300c2c3.md +++ b/gcc/config/rs6000/e300c2c3.md @@ -90,7 +90,7 @@ ;; Other one cycle IU insns (define_insn_reservation "ppce300c3_iu" 1 - (and (eq_attr "type" "integer,insert_word,isel") + (and (eq_attr "type" "integer,insert,isel") (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire") diff --git a/gcc/config/rs6000/e500mc.md b/gcc/config/rs6000/e500mc.md index 051394eaeeb..426903de792 100644 --- a/gcc/config/rs6000/e500mc.md +++ b/gcc/config/rs6000/e500mc.md @@ -70,7 +70,7 @@ ;; Simple SU insns. (define_insn_reservation "e500mc_su" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\ + (and (eq_attr "type" "integer,insert,cmp,compare,\ delayed_compare,var_delayed_compare,fast_compare,\ shift,trap,var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "ppce500mc")) diff --git a/gcc/config/rs6000/e500mc64.md b/gcc/config/rs6000/e500mc64.md index 3fcd94ee6f9..584aef3ea56 100644 --- a/gcc/config/rs6000/e500mc64.md +++ b/gcc/config/rs6000/e500mc64.md @@ -69,7 +69,7 @@ ;; Simple SU insns. (define_insn_reservation "e500mc64_su" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\ + (and (eq_attr "type" "integer,insert,delayed_compare,\ shift,cntlz,exts") (eq_attr "cpu" "ppce500mc64")) "e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire") diff --git a/gcc/config/rs6000/e5500.md b/gcc/config/rs6000/e5500.md index b04d0a3b75a..fd79ca55851 100644 --- a/gcc/config/rs6000/e5500.md +++ b/gcc/config/rs6000/e5500.md @@ -56,7 +56,7 @@ ;; SFX. (define_insn_reservation "e5500_sfx" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\ + (and (eq_attr "type" "integer,insert,delayed_compare,\ shift,cntlz,exts") (eq_attr "cpu" "ppce5500")) "e5500_decode,e5500_sfx") diff --git a/gcc/config/rs6000/e6500.md b/gcc/config/rs6000/e6500.md index 18a372b73af..b84f7038b18 100644 --- a/gcc/config/rs6000/e6500.md +++ b/gcc/config/rs6000/e6500.md @@ -59,7 +59,7 @@ ;; SFX. (define_insn_reservation "e6500_sfx" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,delayed_compare,\ + (and (eq_attr "type" "integer,insert,delayed_compare,\ shift,cntlz,exts") (eq_attr "cpu" "ppce6500")) "e6500_decode,e6500_sfx") diff --git a/gcc/config/rs6000/mpc.md b/gcc/config/rs6000/mpc.md index 317d064b0ad..c4dff563bec 100644 --- a/gcc/config/rs6000/mpc.md +++ b/gcc/config/rs6000/mpc.md @@ -41,7 +41,7 @@ "lsu_mpc") (define_insn_reservation "mpccore-integer" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ + (and (eq_attr "type" "integer,insert,shift,trap,\ var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "mpccore")) "iu_mpc") diff --git a/gcc/config/rs6000/power4.md b/gcc/config/rs6000/power4.md index 2f508510b09..f905a0d0db4 100644 --- a/gcc/config/rs6000/power4.md +++ b/gcc/config/rs6000/power4.md @@ -210,8 +210,10 @@ ; Integer latency is 2 cycles (define_insn_reservation "power4-integer" 2 - (and (eq_attr "type" "integer,insert_dword,shift,trap,\ - var_shift_rotate,cntlz,exts,isel") + (and (ior (eq_attr "type" "integer,shift,trap,\ + var_shift_rotate,cntlz,exts,isel") + (and (eq_attr "type" "insert") + (eq_attr "size" "64"))) (eq_attr "cpu" "power4")) "iq_power4") @@ -238,7 +240,8 @@ |(iu1_power4,nothing,iu1_power4,nothing,iu2_power4))") (define_insn_reservation "power4-insert" 4 - (and (eq_attr "type" "insert_word") + (and (eq_attr "type" "insert") + (eq_attr "size" "32") (eq_attr "cpu" "power4")) "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ ((iu1_power4,nothing,iu2_power4)\ diff --git a/gcc/config/rs6000/power5.md b/gcc/config/rs6000/power5.md index 3b855d3ec68..407ec71159b 100644 --- a/gcc/config/rs6000/power5.md +++ b/gcc/config/rs6000/power5.md @@ -166,8 +166,10 @@ ; Integer latency is 2 cycles (define_insn_reservation "power5-integer" 2 - (and (eq_attr "type" "integer,insert_dword,shift,trap,\ - var_shift_rotate,cntlz,exts,isel,popcnt") + (and (ior (eq_attr "type" "integer,shift,trap,\ + var_shift_rotate,cntlz,exts,isel,popcnt") + (and (eq_attr "type" "insert") + (eq_attr "size" "64"))) (eq_attr "cpu" "power5")) "iq_power5") @@ -194,7 +196,8 @@ |(iu1_power5,nothing,iu2_power5,nothing,iu2_power5))") (define_insn_reservation "power5-insert" 4 - (and (eq_attr "type" "insert_word") + (and (eq_attr "type" "insert") + (eq_attr "size" "32") (eq_attr "cpu" "power5")) "du1_power5+du2_power5,iu1_power5,nothing,iu2_power5") diff --git a/gcc/config/rs6000/power6.md b/gcc/config/rs6000/power6.md index bed2f9f6f11..3a77fc52c97 100644 --- a/gcc/config/rs6000/power6.md +++ b/gcc/config/rs6000/power6.md @@ -247,12 +247,14 @@ "FXU_power6") (define_insn_reservation "power6-insert" 1 - (and (eq_attr "type" "insert_word") + (and (eq_attr "type" "insert") + (eq_attr "size" "32") (eq_attr "cpu" "power6")) "FX2_power6") (define_insn_reservation "power6-insert-dword" 1 - (and (eq_attr "type" "insert_dword") + (and (eq_attr "type" "insert") + (eq_attr "size" "64") (eq_attr "cpu" "power6")) "FX2_power6") diff --git a/gcc/config/rs6000/power7.md b/gcc/config/rs6000/power7.md index be92bd5691c..d6ddc2434c6 100644 --- a/gcc/config/rs6000/power7.md +++ b/gcc/config/rs6000/power7.md @@ -174,7 +174,7 @@ ; FX Unit (define_insn_reservation "power7-integer" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ + (and (eq_attr "type" "integer,insert,shift,trap,\ var_shift_rotate,exts,isel,popcnt") (eq_attr "cpu" "power7")) "DU_power7,FXU_power7") diff --git a/gcc/config/rs6000/power8.md b/gcc/config/rs6000/power8.md index 024b97235d8..f7bd9f86087 100644 --- a/gcc/config/rs6000/power8.md +++ b/gcc/config/rs6000/power8.md @@ -168,7 +168,7 @@ ; FX Unit (define_insn_reservation "power8-1cyc" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ + (and (eq_attr "type" "integer,insert,shift,trap,\ var_shift_rotate,exts,isel") (eq_attr "cpu" "power8")) "DU_any_power8,FXU_power8") diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index ba8479822c5..c8aba1fbcf3 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -26240,8 +26240,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) case TYPE_FAST_COMPARE: case TYPE_EXTS: case TYPE_SHIFT: - case TYPE_INSERT_WORD: - case TYPE_INSERT_DWORD: + case TYPE_INSERT: { if (! store_data_bypass_p (dep_insn, insn)) return 3; @@ -26311,8 +26310,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) case TYPE_FAST_COMPARE: case TYPE_EXTS: case TYPE_SHIFT: - case TYPE_INSERT_WORD: - case TYPE_INSERT_DWORD: + case TYPE_INSERT: { if (set_to_load_agen (dep_insn, insn)) return 3; @@ -26495,7 +26493,8 @@ is_cracked_insn (rtx insn) || (type == TYPE_MUL && get_attr_dot (insn) == DOT_YES) || type == TYPE_IDIV || type == TYPE_LDIV - || type == TYPE_INSERT_WORD) + || (type == TYPE_INSERT + && get_attr_size (insn) == SIZE_32)) return true; } @@ -27320,7 +27319,6 @@ insn_must_be_first_in_group (rtx insn) switch (type) { - case TYPE_INSERT_DWORD: case TYPE_EXTS: case TYPE_CNTLZ: case TYPE_SHIFT: @@ -27328,7 +27326,7 @@ insn_must_be_first_in_group (rtx insn) case TYPE_TRAP: case TYPE_MUL: case TYPE_IDIV: - case TYPE_INSERT_WORD: + case TYPE_INSERT: case TYPE_DELAYED_COMPARE: case TYPE_FPCOMPARE: case TYPE_MFCR: diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 5993537e280..0150e435a37 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -159,7 +159,7 @@ ;; computations. (define_attr "type" "integer,two,three, - shift,var_shift_rotate,insert_word,insert_dword, + shift,var_shift_rotate,insert, mul,halfmul,idiv,ldiv, exts,cntlz,popcnt,isel, load,store,fpload,fpstore,vecload,vecstore, @@ -175,7 +175,7 @@ (const_string "integer")) ;; What data size does this instruction work on? -;; This is used for mul. +;; This is used for insert, mul. (define_attr "size" "8,16,32,64" (const_string "32")) ;; Is this instruction record form ("dot", signed compare to 0, writing CR0)? @@ -3417,7 +3417,7 @@ operands[1] = GEN_INT (start + size - 1); return \"rlwimi %0,%3,%h4,%h2,%h1\"; }" - [(set_attr "type" "insert_word")]) + [(set_attr "type" "insert")]) (define_insn "*insvsi_internal1" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") @@ -3436,7 +3436,7 @@ operands[1] = GEN_INT (start + size - 1); return \"rlwimi %0,%3,%h4,%h2,%h1\"; }" - [(set_attr "type" "insert_word")]) + [(set_attr "type" "insert")]) (define_insn "*insvsi_internal2" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") @@ -3455,7 +3455,7 @@ operands[1] = GEN_INT (start + size - 1); return \"rlwimi %0,%3,%h4,%h2,%h1\"; }" - [(set_attr "type" "insert_word")]) + [(set_attr "type" "insert")]) (define_insn "*insvsi_internal3" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") @@ -3474,7 +3474,7 @@ operands[1] = GEN_INT (start + size - 1); return \"rlwimi %0,%3,%h4,%h2,%h1\"; }" - [(set_attr "type" "insert_word")]) + [(set_attr "type" "insert")]) (define_insn "*insvsi_internal4" [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") @@ -3496,7 +3496,7 @@ operands[1] = GEN_INT (insert_start + insert_size - 1); return \"rlwimi %0,%3,%h5,%h2,%h1\"; }" - [(set_attr "type" "insert_word")]) + [(set_attr "type" "insert")]) ;; combine patterns for rlwimi (define_insn "*insvsi_internal5" @@ -3516,7 +3516,7 @@ operands[1] = GEN_INT(me); return \"rlwimi %0,%3,%h4,%h2,%h1\"; }" - [(set_attr "type" "insert_word")]) + [(set_attr "type" "insert")]) (define_insn "*insvsi_internal6" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -3535,7 +3535,7 @@ operands[1] = GEN_INT(me); return \"rlwimi %0,%3,%h4,%h2,%h1\"; }" - [(set_attr "type" "insert_word")]) + [(set_attr "type" "insert")]) (define_insn "insvdi_internal" [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") @@ -3551,7 +3551,8 @@ operands[1] = GEN_INT (64 - start - size); return \"rldimi %0,%3,%H1,%H2\"; }" - [(set_attr "type" "insert_dword")]) + [(set_attr "type" "insert") + (set_attr "size" "64")]) (define_insn "*insvdi_internal2" [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") diff --git a/gcc/config/rs6000/rs64.md b/gcc/config/rs6000/rs64.md index 76113e873af..aaddb5979d6 100644 --- a/gcc/config/rs6000/rs64.md +++ b/gcc/config/rs6000/rs64.md @@ -46,7 +46,7 @@ "lsu_rs64") (define_insn_reservation "rs64a-integer" 1 - (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ + (and (eq_attr "type" "integer,insert,shift,trap,\ var_shift_rotate,cntlz,exts,isel") (eq_attr "cpu" "rs64a")) "iu_rs64") diff --git a/gcc/config/rs6000/titan.md b/gcc/config/rs6000/titan.md index 21186a3a206..6c7516d3bb2 100644 --- a/gcc/config/rs6000/titan.md +++ b/gcc/config/rs6000/titan.md @@ -51,7 +51,7 @@ (define_bypass 2 "titan_mulhw" "titan_mulhw") (define_insn_reservation "titan_fxu_shift_and_rotate" 2 - (and (eq_attr "type" "insert_word,shift,var_shift_rotate,cntlz") + (and (eq_attr "type" "insert,shift,var_shift_rotate,cntlz") (eq_attr "cpu" "titan")) "titan_issue,titan_fxu_sh,nothing*2,titan_fxu_wb")