[Patch ARM] Add "type" attribute to Everything!
gcc/ * config/arm/types.md: Add "no_insn", "multiple" and "untyped" types. * config/arm/arm-fixed.md: Add type attribute to all insn patterns. * config/arm/vfp.md: Add type attribute to all insn patterns. * config/arm/arm.md: Add type attribute to all insn patterns. * config/arm/thumb2.md: Add type attribute to all insn patterns. * config/arm/arm1020e.md: Update with new attributes. * config/arm/arm1026ejs.md: Update with new attributes. * config/arm/arm1136jfs.md: Update with new attributes. * config/arm/arm926ejs.md: Update with new attributes. * config/arm/cortex-a15.md: Update with new attributes. * config/arm/cortex-a5.md: Update with new attributes. * config/arm/cortex-a53.md: Update with new attributes. * config/arm/cortex-a7.md: Update with new attributes. * config/arm/cortex-a8.md: Update with new attributes. * config/arm/cortex-a9.md: Update with new attributes. * config/arm/cortex-m4.md: Update with new attributes. * config/arm/cortex-r4.md: Update with new attributes. * config/arm/fa526.md: Update with new attributes. * config/arm/fa606te.md: Update with new attributes. * config/arm/fa626te.md: Update with new attributes. * config/arm/fa726te.md: Update with new attributes. From-SVN: r202323
This commit is contained in:
James Greenhalgh
James Greenhalgh
parent
1c83b6738a
commit
594726e49e
264
gcc/ChangeLog
264
gcc/ChangeLog
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@ -1,3 +1,267 @@
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2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
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* config/arm/types.md: Add "no_insn", "multiple" and "untyped"
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types.
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* config/arm/arm-fixed.md: Add type attribute to all insn
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patterns.
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(add<mode>3): Add type attribute.
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(add<mode>3): Likewise.
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(usadd<mode>3): Likewise.
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(ssadd<mode>3): Likewise.
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(sub<mode>3): Likewise.
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(sub<mode>3): Likewise.
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(ussub<mode>3): Likewise.
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(sssub<mode>3): Likewise.
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(ssmulsa3): Likewise.
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(usmulusa3): Likewise.
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(arm_usatsihi): Likewise.
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* config/arm/vfp.md
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(*movdi_vfp): Add types for all instructions.
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(*movdi_vfp_cortexa8): Likewise.
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(*movhf_vfp_neon): Likewise.
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(*movhf_vfp): Likewise.
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(*movdf_vfp): Likewise.
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(*thumb2_movdf_vfp): Likewise.
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(*thumb2_movdfcc_vfp): Likewise.
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* config/arm/arm.md: Add type attribute to all insn patterns.
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(*thumb1_adddi3): Add type attribute.
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(*arm_adddi3): Likewise.
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(*adddi_sesidi_di): Likewise.
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(*adddi_zesidi_di): Likewise.
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(*thumb1_addsi3): Likewise.
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(addsi3_compare0): Likewise.
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(*addsi3_compare0_scratch): Likewise.
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(*compare_negsi_si): Likewise.
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(cmpsi2_addneg): Likewise.
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(*addsi3_carryin_<optab>): Likewise.
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(*addsi3_carryin_alt2_<optab>): Likewise.
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(*addsi3_carryin_clobercc_<optab>): Likewise.
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(*subsi3_carryin): Likewise.
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(*subsi3_carryin_const): Likewise.
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(*subsi3_carryin_compare): Likewise.
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(*subsi3_carryin_compare_const): Likewise.
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(*arm_subdi3): Likewise.
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(*thumb_subdi3): Likewise.
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(*subdi_di_zesidi): Likewise.
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(*subdi_di_sesidi): Likewise.
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(*subdi_zesidi_di): Likewise.
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(*subdi_sesidi_di): Likewise.
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(*subdi_zesidi_ze): Likewise.
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(thumb1_subsi3_insn): Likewise.
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(*arm_subsi3_insn): Likewise.
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(*anddi3_insn): Likewise.
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(*anddi_zesidi_di): Likewise.
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(*anddi_sesdi_di): Likewise.
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(*ne_zeroextracts): Likewise.
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(*ne_zeroextracts): Likewise.
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(*ite_ne_zeroextr): Likewise.
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(*ite_ne_zeroextr): Likewise.
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(*anddi_notdi_di): Likewise.
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(*anddi_notzesidi): Likewise.
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(*anddi_notsesidi): Likewise.
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(andsi_notsi_si): Likewise.
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(thumb1_bicsi3): Likewise.
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(*iordi3_insn): Likewise.
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(*iordi_zesidi_di): Likewise.
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(*iordi_sesidi_di): Likewise.
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(*thumb1_iorsi3_insn): Likewise.
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(*xordi3_insn): Likewise.
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(*xordi_zesidi_di): Likewise.
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(*xordi_sesidi_di): Likewise.
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(*arm_xorsi3): Likewise.
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(*andsi_iorsi3_no): Likewise.
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(*smax_0): Likewise.
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(*smax_m1): Likewise.
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(*arm_smax_insn): Likewise.
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(*smin_0): Likewise.
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(*arm_smin_insn): Likewise.
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(*arm_umaxsi3): Likewise.
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(*arm_uminsi3): Likewise.
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(*minmax_arithsi): Likewise.
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(*minmax_arithsi_): Likewise.
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(*satsi_<SAT:code>): Likewise.
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(arm_ashldi3_1bit): Likewise.
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(arm_ashrdi3_1bit): Likewise.
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(arm_lshrdi3_1bit): Likewise.
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(*arm_negdi2): Likewise.
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(*thumb1_negdi2): Likewise.
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(*arm_negsi2): Likewise.
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(*thumb1_negsi2): Likewise.
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(*negdi_extendsid): Likewise.
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(*negdi_zero_extend): Likewise.
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(*arm_abssi2): Likewise.
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(*thumb1_abssi2): Likewise.
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(*arm_neg_abssi2): Likewise.
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(*thumb1_neg_abss): Likewise.
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(one_cmpldi2): Likewise.
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(extend<mode>di2): Likewise.
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(*compareqi_eq0): Likewise.
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(*arm_extendhisi2addsi): Likewise.
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(*arm_movdi): Likewise.
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(*thumb1_movdi_insn): Likewise.
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(*arm_movt): Likewise.
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(*thumb1_movsi_insn): Likewise.
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(pic_add_dot_plus_four): Likewise.
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(pic_add_dot_plus_eight): Likewise.
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(tls_load_dot_plus_eight): Likewise.
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(*thumb1_movhi_insn): Likewise.
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(*thumb1_movsf_insn): Likewise.
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(*movdf_soft_insn): Likewise.
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(*thumb_movdf_insn): Likewise.
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(cbranchsi4_insn): Likewise.
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(cbranchsi4_scratch): Likewise.
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(*negated_cbranchsi4): Likewise.
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(*tbit_cbranch): Likewise.
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(*tlobits_cbranch): Likewise.
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(*tstsi3_cbranch): Likewise.
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(*cbranchne_decr1): Likewise.
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(*addsi3_cbranch): Likewise.
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(*addsi3_cbranch_scratch): Likewise.
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(*arm_cmpdi_insn): Likewise.
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(*arm_cmpdi_unsig): Likewise.
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(*arm_cmpdi_zero): Likewise.
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(*thumb_cmpdi_zero): Likewise.
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(*deleted_compare): Likewise.
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(*mov_scc): Likewise.
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(*mov_negscc): Likewise.
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(*mov_notscc): Likewise.
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(*cstoresi_eq0_thumb1_insn): Likewise.
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(cstoresi_nltu_thumb1): Likewise.
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(cstoresi_ltu_thu): Likewise.
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(thumb1_addsi3_addgeu): Likewise.
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(*arm_jump): Likewise.
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(*thumb_jump): Likewise.
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(*check_arch2): Likewise.
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(arm_casesi_internal): Likewise.
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(thumb1_casesi_dispatch): Likewise.
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(*arm_indirect_jump): Likewise.
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(*thumb1_indirect_jump): Likewise.
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(nop): Likewise.
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(*and_scc): Likewise.
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(*ior_scc): Likewise.
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(*compare_scc): Likewise.
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(*cond_move): Likewise.
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(*cond_arith): Likewise.
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(*cond_sub): Likewise.
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(*cmp_ite0): Likewise.
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(*cmp_ite1): Likewise.
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(*cmp_and): Likewise.
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(*cmp_ior): Likewise.
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(*ior_scc_scc): Likewise.
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(*ior_scc_scc_cmp): Likewise.
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(*and_scc_scc): Likewise.
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(*and_scc_scc_cmp): Likewise.
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(*and_scc_scc_nod): Likewise.
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(*negscc): Likewise.
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(movcond_addsi): Likewise.
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(movcond): Likewise.
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(*ifcompare_plus_move): Likewise.
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(*if_plus_move): Likewise.
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(*ifcompare_move_plus): Likewise.
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(*if_move_plus): Likewise.
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(*ifcompare_arith_arith): Likewise.
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(*if_arith_arith): Likewise.
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(*ifcompare_arith_move): Likewise.
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(*if_arith_move): Likewise.
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(*ifcompare_move_arith): Likewise.
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(*if_move_arith): Likewise.
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(*ifcompare_move_not): Likewise.
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(*if_move_not): Likewise.
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(*ifcompare_not_move): Likewise.
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(*if_not_move): Likewise.
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(*ifcompare_shift_move): Likewise.
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(*if_shift_move): Likewise.
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(*ifcompare_move_shift): Likewise.
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(*if_move_shift): Likewise.
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(*ifcompare_shift_shift): Likewise.
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(*ifcompare_not_arith): Likewise.
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(*ifcompare_arith_not): Likewise.
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(*if_arith_not): Likewise.
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(*ifcompare_neg_move): Likewise.
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(*if_neg_move): Likewise.
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(*ifcompare_move_neg): Likewise.
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(*if_move_neg): Likewise.
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(prologue_thumb1_interwork): Likewise.
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(*cond_move_not): Likewise.
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(*sign_extract_onebit): Likewise.
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(*not_signextract_onebit): Likewise.
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(stack_tie): Likewise.
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(align_4): Likewise.
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(align_8): Likewise.
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(consttable_end): Likewise.
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(consttable_1): Likewise.
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(consttable_2): Likewise.
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(consttable_4): Likewise.
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(consttable_8): Likewise.
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(consttable_16): Likewise.
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(*thumb1_tablejump): Likewise.
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(prefetch): Likewise.
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(force_register_use): Likewise.
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(thumb_eh_return): Likewise.
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(load_tp_hard): Likewise.
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(load_tp_soft): Likewise.
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(tlscall): Likewise.
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(*arm_movtas_ze): Likewise.
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(*arm_rev): Likewise.
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(*arm_revsh): Likewise.
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(*arm_rev16): Likewise.
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* config/arm/thumb2.md
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(*thumb2_smaxsi3): Likewise.
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(*thumb2_sminsi3): Likewise.
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(*thumb32_umaxsi3): Likewise.
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(*thumb2_uminsi3): Likewise.
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(*thumb2_negdi2): Likewise.
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(*thumb2_abssi2): Likewise.
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(*thumb2_neg_abss): Likewise.
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(*thumb2_movsi_insn): Likewise.
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(tls_load_dot_plus_four): Likewise.
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(*thumb2_movhi_insn): Likewise.
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(*thumb2_mov_scc): Likewise.
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(*thumb2_mov_negs): Likewise.
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(*thumb2_mov_negs): Likewise.
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(*thumb2_mov_nots): Likewise.
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(*thumb2_mov_nots): Likewise.
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(*thumb2_movsicc_): Likewise.
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(*thumb2_movsfcc_soft_insn): Likewise.
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(*thumb2_indirect_jump): Likewise.
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(*thumb2_and_scc): Likewise.
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(*thumb2_ior_scc): Likewise.
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(*thumb2_ior_scc_strict_it): Likewise.
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(*thumb2_cond_move): Likewise.
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(*thumb2_cond_arith): Likewise.
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(*thumb2_cond_ari): Likewise.
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(*thumb2_cond_sub): Likewise.
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(*thumb2_negscc): Likewise.
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(*thumb2_movcond): Likewise.
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(thumb2_casesi_internal): Likewise.
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(thumb2_casesi_internal_pic): Likewise.
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(*thumb2_alusi3_short): Likewise.
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(*thumb2_mov<mode>_shortim): Likewise.
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(*thumb2_addsi_short): Likewise.
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(*thumb2_subsi_short): Likewise.
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(thumb2_addsi3_compare0): Likewise.
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(*thumb2_cbz): Likewise.
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(*thumb2_cbnz): Likewise.
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(*thumb2_one_cmplsi2_short): Likewise.
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(*thumb2_negsi2_short): Likewise.
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(*orsi_notsi_si): Likewise.
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* config/arm/arm1020e.md: Update with new attributes.
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* config/arm/arm1026ejs.md: Update with new attributes.
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* config/arm/arm1136jfs.md: Update with new attributes.
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* config/arm/arm926ejs.md: Update with new attributes.
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* config/arm/cortex-a15.md: Update with new attributes.
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* config/arm/cortex-a5.md: Update with new attributes.
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* config/arm/cortex-a53.md: Update with new attributes.
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* config/arm/cortex-a7.md: Update with new attributes.
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* config/arm/cortex-a8.md: Update with new attributes.
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* config/arm/cortex-a9.md: Update with new attributes.
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* config/arm/cortex-m4.md: Update with new attributes.
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* config/arm/cortex-r4.md: Update with new attributes.
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* config/arm/fa526.md: Update with new attributes.
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* config/arm/fa606te.md: Update with new attributes.
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* config/arm/fa626te.md: Update with new attributes.
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* config/arm/fa726te.md: Update with new attributes.
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2013-09-06 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-simd.md
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@ -25,7 +25,8 @@
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"TARGET_32BIT"
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"add%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "yes,no")])
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(set_attr "predicable_short_it" "yes,no")
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(set_attr "type" "alu_reg")])
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(define_insn "add<mode>3"
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[(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
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@ -34,7 +35,8 @@
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"TARGET_INT_SIMD"
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"sadd<qaddsub_suf>%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")])
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(set_attr "predicable_short_it" "no")
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(set_attr "type" "alu_reg")])
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(define_insn "usadd<mode>3"
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[(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
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@ -43,7 +45,8 @@
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"TARGET_INT_SIMD"
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"uqadd<qaddsub_suf>%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")])
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(set_attr "predicable_short_it" "no")
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(set_attr "type" "alu_reg")])
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(define_insn "ssadd<mode>3"
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[(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
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@ -52,7 +55,8 @@
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"TARGET_INT_SIMD"
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"qadd<qaddsub_suf>%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")])
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(set_attr "predicable_short_it" "no")
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(set_attr "type" "alu_reg")])
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(define_insn "sub<mode>3"
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[(set (match_operand:FIXED 0 "s_register_operand" "=l,r")
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@ -61,7 +65,8 @@
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"TARGET_32BIT"
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"sub%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "yes,no")])
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(set_attr "predicable_short_it" "yes,no")
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(set_attr "type" "alu_reg")])
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(define_insn "sub<mode>3"
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[(set (match_operand:ADDSUB 0 "s_register_operand" "=r")
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@ -70,7 +75,8 @@
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"TARGET_INT_SIMD"
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"ssub<qaddsub_suf>%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")])
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(set_attr "predicable_short_it" "no")
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(set_attr "type" "alu_reg")])
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(define_insn "ussub<mode>3"
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[(set (match_operand:UQADDSUB 0 "s_register_operand" "=r")
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@ -80,7 +86,8 @@
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"TARGET_INT_SIMD"
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"uqsub<qaddsub_suf>%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")])
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(set_attr "predicable_short_it" "no")
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(set_attr "type" "alu_reg")])
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(define_insn "sssub<mode>3"
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[(set (match_operand:QADDSUB 0 "s_register_operand" "=r")
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@ -89,7 +96,8 @@
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"TARGET_INT_SIMD"
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"qsub<qaddsub_suf>%?\\t%0, %1, %2"
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")])
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(set_attr "predicable_short_it" "no")
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(set_attr "type" "alu_reg")])
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;; Fractional multiplies.
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@ -246,6 +254,7 @@
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return "";
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}
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[(set_attr "conds" "clob")
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(set_attr "type" "multiple")
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(set (attr "length")
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(if_then_else (eq_attr "is_thumb" "yes")
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(if_then_else (match_test "arm_restrict_it")
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@ -305,6 +314,7 @@
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return "";
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}
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[(set_attr "conds" "clob")
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(set_attr "type" "multiple")
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(set (attr "length")
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(if_then_else (eq_attr "is_thumb" "yes")
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(if_then_else (match_test "arm_restrict_it")
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@ -414,5 +424,6 @@
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"TARGET_INT_SIMD"
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"usat%?\\t%0, #16, %1"
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[(set_attr "predicable" "yes")
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(set_attr "predicable_short_it" "no")]
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(set_attr "predicable_short_it" "no")
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(set_attr "type" "alu_imm")]
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)
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File diff suppressed because it is too large
Load Diff
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@ -71,7 +71,8 @@
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adc_imm,adcs_imm,adc_reg,adcs_reg,\
|
||||
adr,bfm,rev,\
|
||||
shift_imm,shift_reg,\
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg"))
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg,\
|
||||
multiple,no_insn"))
|
||||
"1020a_e,1020a_m,1020a_w")
|
||||
|
||||
;; ALU operations with a shift-by-constant operand
|
||||
|
|
|
|||
|
|
@ -71,7 +71,8 @@
|
|||
adc_imm,adcs_imm,adc_reg,adcs_reg,\
|
||||
adr,bfm,rev,\
|
||||
shift_imm,shift_reg,\
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg"))
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg,\
|
||||
multiple,no_insn"))
|
||||
"a_e,a_m,a_w")
|
||||
|
||||
;; ALU operations with a shift-by-constant operand
|
||||
|
|
|
|||
|
|
@ -80,7 +80,8 @@
|
|||
adc_imm,adcs_imm,adc_reg,adcs_reg,\
|
||||
adr,bfm,rev,\
|
||||
shift_imm,shift_reg,\
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg"))
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg,\
|
||||
multiple,no_insn"))
|
||||
"e_1,e_2,e_3,e_wb")
|
||||
|
||||
;; ALU operations with a shift-by-constant operand
|
||||
|
|
|
|||
|
|
@ -66,7 +66,8 @@
|
|||
logic_shift_imm,logics_shift_imm,\
|
||||
shift_imm,shift_reg,extend,\
|
||||
mov_imm,mov_reg,mov_shift,\
|
||||
mvn_imm,mvn_reg,mvn_shift"))
|
||||
mvn_imm,mvn_reg,mvn_shift,\
|
||||
multiple,no_insn"))
|
||||
"e,m,w")
|
||||
|
||||
;; ALU operations with a shift-by-register operand
|
||||
|
|
|
|||
|
|
@ -67,7 +67,8 @@
|
|||
adr,bfm,rev,\
|
||||
shift_imm,shift_reg,\
|
||||
mov_imm,mov_reg,\
|
||||
mvn_imm,mvn_reg"))
|
||||
mvn_imm,mvn_reg,\
|
||||
multiple,no_insn"))
|
||||
"ca15_issue1,(ca15_sx1,ca15_sx1_alu)|(ca15_sx2,ca15_sx2_alu)")
|
||||
|
||||
;; ALU ops with immediate shift
|
||||
|
|
|
|||
|
|
@ -63,7 +63,8 @@
|
|||
adc_imm,adcs_imm,adc_reg,adcs_reg,\
|
||||
adr,bfm,rev,\
|
||||
shift_imm,shift_reg,\
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg"))
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg,\
|
||||
multiple,no_insn"))
|
||||
"cortex_a5_ex1")
|
||||
|
||||
(define_insn_reservation "cortex_a5_alu_shift" 2
|
||||
|
|
|
|||
|
|
@ -72,7 +72,8 @@
|
|||
adc_imm,adcs_imm,adc_reg,adcs_reg,\
|
||||
adr,bfm,csel,rev,\
|
||||
shift_imm,shift_reg,\
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg"))
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg,\
|
||||
multiple,no_insn"))
|
||||
"cortex_a53_slot_any")
|
||||
|
||||
(define_insn_reservation "cortex_a53_alu_shift" 2
|
||||
|
|
@ -81,7 +82,7 @@
|
|||
logic_shift_imm,logics_shift_imm,\
|
||||
alu_shift_reg,alus_shift_reg,\
|
||||
logic_shift_reg,logics_shift_reg,\
|
||||
mov_shift,mov_shift_reg,\
|
||||
extend,mov_shift,mov_shift_reg,\
|
||||
mvn_shift,mvn_shift_reg"))
|
||||
"cortex_a53_slot_any")
|
||||
|
||||
|
|
|
|||
|
|
@ -109,7 +109,8 @@
|
|||
alu_shift_reg,alus_shift_reg,\
|
||||
logic_shift_reg,logics_shift_reg,\
|
||||
mov_shift,mov_shift_reg,\
|
||||
mvn_shift,mvn_shift_reg"))
|
||||
mvn_shift,mvn_shift_reg,\
|
||||
multiple,no_insn"))
|
||||
"cortex_a7_ex1")
|
||||
|
||||
;; Forwarding path for unshifted operands.
|
||||
|
|
|
|||
|
|
@ -89,7 +89,8 @@
|
|||
alu_reg,alus_reg,logic_reg,logics_reg,\
|
||||
adc_imm,adcs_imm,adc_reg,adcs_reg,\
|
||||
adr,bfm,clz,rbit,rev,\
|
||||
shift_imm,shift_reg"))
|
||||
shift_imm,shift_reg,\
|
||||
multiple,no_insn"))
|
||||
"cortex_a8_default")
|
||||
|
||||
(define_insn_reservation "cortex_a8_alu_shift" 2
|
||||
|
|
|
|||
|
|
@ -86,7 +86,8 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1")
|
|||
adr,bfm,rev,\
|
||||
shift_imm,shift_reg,\
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg,\
|
||||
mov_shift_reg,mov_shift"))
|
||||
mov_shift_reg,mov_shift,\
|
||||
multiple,no_insn"))
|
||||
"cortex_a9_p0_default|cortex_a9_p1_default")
|
||||
|
||||
;; An instruction using the shifter will go down E1.
|
||||
|
|
|
|||
|
|
@ -41,7 +41,8 @@
|
|||
alu_shift_reg,alus_shift_reg,\
|
||||
logic_shift_reg,logics_shift_reg,\
|
||||
mov_imm,mov_reg,mov_shift,mov_shift_reg,\
|
||||
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg")
|
||||
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
|
||||
multiple,no_insn")
|
||||
(ior (eq_attr "mul32" "yes")
|
||||
(eq_attr "mul64" "yes"))))
|
||||
"cortex_m4_ex")
|
||||
|
|
|
|||
|
|
@ -101,7 +101,8 @@
|
|||
(and (eq_attr "tune_cortexr4" "yes")
|
||||
(eq_attr "type" "alu_shift_reg,alus_shift_reg,\
|
||||
logic_shift_reg,logics_shift_reg,\
|
||||
mov_shift_reg,mvn_shift_reg"))
|
||||
mov_shift_reg,mvn_shift_reg,\
|
||||
multiple,no_insn"))
|
||||
"cortex_r4_alu_shift_reg")
|
||||
|
||||
;; An ALU instruction followed by an ALU instruction with no early dep.
|
||||
|
|
|
|||
|
|
@ -67,7 +67,8 @@
|
|||
adc_imm,adcs_imm,adc_reg,adcs_reg,\
|
||||
adr,bfm,rev,\
|
||||
shift_imm,shift_reg,\
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg"))
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg,\
|
||||
multiple,no_insn"))
|
||||
"fa526_core")
|
||||
|
||||
(define_insn_reservation "526_alu_shift_op" 2
|
||||
|
|
|
|||
|
|
@ -72,7 +72,8 @@
|
|||
alu_shift_reg,alus_shift_reg,\
|
||||
logic_shift_reg,logics_shift_reg,\
|
||||
mov_imm,mov_reg,mov_shift,mov_shift_reg,\
|
||||
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg"))
|
||||
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
|
||||
multiple,no_insn"))
|
||||
"fa606te_core")
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
|
|
|
|||
|
|
@ -73,7 +73,8 @@
|
|||
adc_imm,adcs_imm,adc_reg,adcs_reg,\
|
||||
adr,bfm,rev,\
|
||||
shift_imm,shift_reg,\
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg"))
|
||||
mov_imm,mov_reg,mvn_imm,mvn_reg,\
|
||||
multiple,no_insn"))
|
||||
"fa626te_core")
|
||||
|
||||
(define_insn_reservation "626te_alu_shift_op" 2
|
||||
|
|
|
|||
|
|
@ -90,7 +90,8 @@
|
|||
alu_reg,alus_reg,logic_reg,logics_reg,\
|
||||
adc_imm,adcs_imm,adc_reg,adcs_reg,\
|
||||
adr,bfm,rev,\
|
||||
shift_imm,shift_reg"))
|
||||
shift_imm,shift_reg,\
|
||||
multiple,no_insn"))
|
||||
"fa726te_issue+(fa726te_alu0_pipe|fa726te_alu1_pipe)")
|
||||
|
||||
;; ALU operations with a shift-by-register operand.
|
||||
|
|
|
|||
|
|
@ -58,7 +58,8 @@
|
|||
""
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "enabled_for_depr_it" "yes,yes,no")
|
||||
(set_attr "length" "6,6,10")]
|
||||
(set_attr "length" "6,6,10")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*thumb2_sminsi3"
|
||||
|
|
@ -78,7 +79,8 @@
|
|||
""
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "enabled_for_depr_it" "yes,yes,no")
|
||||
(set_attr "length" "6,6,10")]
|
||||
(set_attr "length" "6,6,10")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*thumb32_umaxsi3"
|
||||
|
|
@ -98,7 +100,8 @@
|
|||
""
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "length" "6,6,10")
|
||||
(set_attr "enabled_for_depr_it" "yes,yes,no")]
|
||||
(set_attr "enabled_for_depr_it" "yes,yes,no")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*thumb2_uminsi3"
|
||||
|
|
@ -118,7 +121,8 @@
|
|||
""
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "length" "6,6,10")
|
||||
(set_attr "enabled_for_depr_it" "yes,yes,no")]
|
||||
(set_attr "enabled_for_depr_it" "yes,yes,no")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
;; Thumb-2 does not have rsc, so use a clever trick with shifter operands.
|
||||
|
|
@ -143,7 +147,8 @@
|
|||
operands[1] = gen_lowpart (SImode, operands[1]);
|
||||
}
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "length" "8")]
|
||||
(set_attr "length" "8")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*thumb2_abssi2"
|
||||
|
|
@ -200,7 +205,8 @@
|
|||
(set_attr "predicable_short_it" "no")
|
||||
(set_attr "enabled_for_depr_it" "yes,yes,no")
|
||||
(set_attr "ce_count" "2")
|
||||
(set_attr "length" "8,6,10")]
|
||||
(set_attr "length" "8,6,10")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*thumb2_neg_abssi2"
|
||||
|
|
@ -257,7 +263,8 @@
|
|||
(set_attr "enabled_for_depr_it" "yes,yes,no")
|
||||
(set_attr "predicable_short_it" "no")
|
||||
(set_attr "ce_count" "2")
|
||||
(set_attr "length" "8,6,10")]
|
||||
(set_attr "length" "8,6,10")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
;; We have two alternatives here for memory loads (and similarly for stores)
|
||||
|
|
@ -282,7 +289,7 @@
|
|||
ldr%?\\t%0, %1
|
||||
str%?\\t%1, %0
|
||||
str%?\\t%1, %0"
|
||||
[(set_attr "type" "*,alu_imm,alu_imm,alu_imm,*,load1,load1,store1,store1")
|
||||
[(set_attr "type" "mov_reg,alu_imm,alu_imm,alu_imm,mov_imm,load1,load1,store1,store1")
|
||||
(set_attr "length" "2,4,2,4,4,4,4,4,4")
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no")
|
||||
|
|
@ -303,7 +310,8 @@
|
|||
INTVAL (operands[3]));
|
||||
return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
|
||||
"
|
||||
[(set_attr "length" "4,4,6,6")]
|
||||
[(set_attr "length" "4,4,6,6")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
|
||||
|
|
@ -319,7 +327,7 @@
|
|||
movw%?\\t%0, %L1\\t%@ movhi
|
||||
str%(h%)\\t%1, %0\\t%@ movhi
|
||||
ldr%(h%)\\t%0, %1\\t%@ movhi"
|
||||
[(set_attr "type" "*,*,store1,load1")
|
||||
[(set_attr "type" "mov_imm,mov_reg,store1,load1")
|
||||
(set_attr "predicable" "yes")
|
||||
(set_attr "pool_range" "*,*,*,4094")
|
||||
(set_attr "neg_pool_range" "*,*,*,250")]
|
||||
|
|
@ -367,7 +375,8 @@
|
|||
""
|
||||
[(set_attr "conds" "use")
|
||||
(set_attr "enabled_for_depr_it" "yes,no")
|
||||
(set_attr "length" "8,10")]
|
||||
(set_attr "length" "8,10")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*thumb2_mov_negscc"
|
||||
|
|
@ -385,7 +394,8 @@
|
|||
operands[3] = GEN_INT (~0);
|
||||
}
|
||||
[(set_attr "conds" "use")
|
||||
(set_attr "length" "10")]
|
||||
(set_attr "length" "10")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*thumb2_mov_negscc_strict_it"
|
||||
|
|
@ -413,7 +423,8 @@
|
|||
|
||||
}
|
||||
[(set_attr "conds" "use")
|
||||
(set_attr "length" "8")]
|
||||
(set_attr "length" "8")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*thumb2_mov_notscc"
|
||||
|
|
@ -432,7 +443,8 @@
|
|||
operands[4] = GEN_INT (~0);
|
||||
}
|
||||
[(set_attr "conds" "use")
|
||||
(set_attr "length" "10")]
|
||||
(set_attr "length" "10")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*thumb2_mov_notscc_strict_it"
|
||||
|
|
@ -454,7 +466,8 @@
|
|||
VOIDmode, operands[2], const0_rtx);
|
||||
}
|
||||
[(set_attr "conds" "use")
|
||||
(set_attr "length" "8")]
|
||||
(set_attr "length" "8")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*thumb2_movsicc_insn"
|
||||
|
|
@ -514,7 +527,8 @@
|
|||
}
|
||||
[(set_attr "length" "4,4,6,6,6,6,10,10,10,10,6")
|
||||
(set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,yes")
|
||||
(set_attr "conds" "use")]
|
||||
(set_attr "conds" "use")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_movsfcc_soft_insn"
|
||||
|
|
@ -528,7 +542,8 @@
|
|||
it\\t%D3\;mov%D3\\t%0, %2
|
||||
it\\t%d3\;mov%d3\\t%0, %1"
|
||||
[(set_attr "length" "6,6")
|
||||
(set_attr "conds" "use")]
|
||||
(set_attr "conds" "use")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn "*call_reg_thumb2"
|
||||
|
|
@ -557,7 +572,8 @@
|
|||
(match_operand:SI 0 "register_operand" "l*r"))]
|
||||
"TARGET_THUMB2"
|
||||
"bx\\t%0"
|
||||
[(set_attr "conds" "clob")]
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "type" "branch")]
|
||||
)
|
||||
;; Don't define thumb2_load_indirect_jump because we can't guarantee label
|
||||
;; addresses will have the thumb bit set correctly.
|
||||
|
|
@ -585,6 +601,7 @@
|
|||
operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
|
||||
}
|
||||
[(set_attr "conds" "use")
|
||||
(set_attr "type" "multiple")
|
||||
(set (attr "length") (if_then_else (match_test "arm_restrict_it")
|
||||
(const_int 8)
|
||||
(const_int 10)))]
|
||||
|
|
@ -617,7 +634,8 @@
|
|||
operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
|
||||
}
|
||||
[(set_attr "conds" "use")
|
||||
(set_attr "length" "6,10")]
|
||||
(set_attr "length" "6,10")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_ior_scc_strict_it"
|
||||
|
|
@ -630,7 +648,8 @@
|
|||
it\\t%d2\;mov%d2\\t%0, #1\;it\\t%d2\;orr%d2\\t%0, %1
|
||||
mov\\t%0, #1\;orr\\t%0, %1\;it\\t%D2\;mov%D2\\t%0, %1"
|
||||
[(set_attr "conds" "use")
|
||||
(set_attr "length" "8")]
|
||||
(set_attr "length" "8")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_cond_move"
|
||||
|
|
@ -679,7 +698,8 @@
|
|||
return \"\";
|
||||
"
|
||||
[(set_attr "conds" "use")
|
||||
(set_attr "length" "6,6,10")]
|
||||
(set_attr "length" "6,6,10")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_cond_arith"
|
||||
|
|
@ -716,7 +736,8 @@
|
|||
return \"%i5%d4\\t%0, %1, #1\";
|
||||
"
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "length" "14")]
|
||||
(set_attr "length" "14")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*thumb2_cond_arith_strict_it"
|
||||
|
|
@ -785,7 +806,8 @@
|
|||
FAIL;
|
||||
}
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "length" "12")]
|
||||
(set_attr "length" "12")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_cond_sub"
|
||||
|
|
@ -816,7 +838,8 @@
|
|||
return \"sub%d4\\t%0, %1, #1\";
|
||||
"
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "length" "10,14")]
|
||||
(set_attr "length" "10,14")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn_and_split "*thumb2_negscc"
|
||||
|
|
@ -884,7 +907,8 @@
|
|||
FAIL;
|
||||
}
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "length" "14")]
|
||||
(set_attr "length" "14")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_movcond"
|
||||
|
|
@ -967,7 +991,8 @@
|
|||
return \"\";
|
||||
"
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "length" "10,10,14")]
|
||||
(set_attr "length" "10,10,14")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
;; Zero and sign extension instructions.
|
||||
|
|
@ -1030,7 +1055,8 @@
|
|||
"TARGET_THUMB2 && !flag_pic"
|
||||
"* return thumb2_output_casesi(operands);"
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "length" "16")]
|
||||
(set_attr "length" "16")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn "thumb2_casesi_internal_pic"
|
||||
|
|
@ -1048,7 +1074,8 @@
|
|||
"TARGET_THUMB2 && flag_pic"
|
||||
"* return thumb2_output_casesi(operands);"
|
||||
[(set_attr "conds" "clob")
|
||||
(set_attr "length" "20")]
|
||||
(set_attr "length" "20")
|
||||
(set_attr "type" "multiple")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_return"
|
||||
|
|
@ -1085,7 +1112,8 @@
|
|||
&& GET_CODE(operands[3]) != MINUS"
|
||||
"%I3%!\\t%0, %1, %2"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "length" "2")]
|
||||
(set_attr "length" "2")
|
||||
(set_attr "type" "alu_reg")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_shiftsi3_short"
|
||||
|
|
@ -1113,7 +1141,8 @@
|
|||
"TARGET_THUMB2 && reload_completed"
|
||||
"mov%!\t%0, %1"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "length" "2")]
|
||||
(set_attr "length" "2")
|
||||
(set_attr "type" "mov_imm")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_addsi_short"
|
||||
|
|
@ -1137,7 +1166,8 @@
|
|||
return \"add%!\\t%0, %1, %2\";
|
||||
"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "length" "2")]
|
||||
(set_attr "length" "2")
|
||||
(set_attr "type" "alu_reg")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_subsi_short"
|
||||
|
|
@ -1148,7 +1178,8 @@
|
|||
"TARGET_THUMB2 && reload_completed"
|
||||
"sub%!\\t%0, %1, %2"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "length" "2")]
|
||||
(set_attr "length" "2")
|
||||
(set_attr "type" "alu_reg")]
|
||||
)
|
||||
|
||||
(define_peephole2
|
||||
|
|
@ -1200,7 +1231,8 @@
|
|||
return \"adds\\t%0, %1, %2\";
|
||||
"
|
||||
[(set_attr "conds" "set")
|
||||
(set_attr "length" "2,2,4")]
|
||||
(set_attr "length" "2,2,4")
|
||||
(set_attr "type" "alu_reg")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_addsi3_compare0_scratch"
|
||||
|
|
@ -1284,7 +1316,8 @@
|
|||
(le (minus (match_dup 1) (pc)) (const_int 128))
|
||||
(not (match_test "which_alternative")))
|
||||
(const_int 2)
|
||||
(const_int 8)))]
|
||||
(const_int 8)))
|
||||
(set_attr "type" "branch,multiple")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_cbnz"
|
||||
|
|
@ -1307,7 +1340,8 @@
|
|||
(le (minus (match_dup 1) (pc)) (const_int 128))
|
||||
(not (match_test "which_alternative")))
|
||||
(const_int 2)
|
||||
(const_int 8)))]
|
||||
(const_int 8)))
|
||||
(set_attr "type" "branch,multiple")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_one_cmplsi2_short"
|
||||
|
|
@ -1317,7 +1351,8 @@
|
|||
"TARGET_THUMB2 && reload_completed"
|
||||
"mvn%!\t%0, %1"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "length" "2")]
|
||||
(set_attr "length" "2")
|
||||
(set_attr "type" "mvn_reg")]
|
||||
)
|
||||
|
||||
(define_insn "*thumb2_negsi2_short"
|
||||
|
|
@ -1327,7 +1362,8 @@
|
|||
"TARGET_THUMB2 && reload_completed"
|
||||
"neg%!\t%0, %1"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "length" "2")]
|
||||
(set_attr "length" "2")
|
||||
(set_attr "type" "alu_reg")]
|
||||
)
|
||||
|
||||
(define_insn "*orsi_notsi_si"
|
||||
|
|
@ -1337,7 +1373,8 @@
|
|||
"TARGET_THUMB2"
|
||||
"orn%?\\t%0, %1, %2"
|
||||
[(set_attr "predicable" "yes")
|
||||
(set_attr "predicable_short_it" "no")]
|
||||
(set_attr "predicable_short_it" "no")
|
||||
(set_attr "type" "logic_reg")]
|
||||
)
|
||||
|
||||
(define_insn "*orsi_not_shiftsi_si"
|
||||
|
|
|
|||
|
|
@ -105,10 +105,14 @@
|
|||
; mov_shift_reg simple MOV instruction, shifted operand by a register.
|
||||
; mul integer multiply.
|
||||
; muls integer multiply, flag setting.
|
||||
; multiple more than one instruction, candidate for future
|
||||
; splitting, or better modeling.
|
||||
; mvn_imm inverting move instruction, immediate.
|
||||
; mvn_reg inverting move instruction, register.
|
||||
; mvn_shift inverting move instruction, shifted operand by a constant.
|
||||
; mvn_shift_reg inverting move instruction, shifted operand by a register.
|
||||
; no_insn an insn which does not represent an instruction in the
|
||||
; final output, thus having no impact on scheduling.
|
||||
; rbit reverse bits.
|
||||
; rev reverse bytes.
|
||||
; sdiv signed division.
|
||||
|
|
@ -150,6 +154,8 @@
|
|||
; umlals unsigned multiply accumulate long, flag setting.
|
||||
; umull unsigned multiply long.
|
||||
; umulls unsigned multiply long, flag setting.
|
||||
; untyped insn without type information - default, and error,
|
||||
; case.
|
||||
;
|
||||
; The classification below is for instructions used by the Wireless MMX
|
||||
; Technology. Each attribute value is used to classify an instruction of the
|
||||
|
|
@ -301,6 +307,7 @@
|
|||
branch,\
|
||||
call,\
|
||||
clz,\
|
||||
no_insn,\
|
||||
csel,\
|
||||
extend,\
|
||||
f_cvt,\
|
||||
|
|
@ -360,10 +367,12 @@
|
|||
mov_shift_reg,\
|
||||
mul,\
|
||||
muls,\
|
||||
multiple,\
|
||||
mvn_imm,\
|
||||
mvn_reg,\
|
||||
mvn_shift,\
|
||||
mvn_shift_reg,\
|
||||
nop,\
|
||||
rbit,\
|
||||
rev,\
|
||||
sdiv,\
|
||||
|
|
@ -403,6 +412,7 @@
|
|||
umlals,\
|
||||
umull,\
|
||||
umulls,\
|
||||
untyped,\
|
||||
wmmx_tandc,\
|
||||
wmmx_tbcst,\
|
||||
wmmx_textrc,\
|
||||
|
|
@ -524,7 +534,7 @@
|
|||
neon_vst2_4_regs_vst3_vst4,\
|
||||
neon_vst3_vst4_lane,\
|
||||
neon_vst3_vst4"
|
||||
(const_string "alu_imm"))
|
||||
(const_string "untyped"))
|
||||
|
||||
; Is this an (integer side) multiply with a 32-bit (or smaller) result?
|
||||
(define_attr "mul32" "no,yes"
|
||||
|
|
|
|||
|
|
@ -144,7 +144,7 @@
|
|||
gcc_unreachable ();
|
||||
}
|
||||
"
|
||||
[(set_attr "type" "*,*,*,*,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
|
||||
[(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
|
||||
(set (attr "length") (cond [(eq_attr "alternative" "1,4,5,6") (const_int 8)
|
||||
(eq_attr "alternative" "2") (const_int 12)
|
||||
(eq_attr "alternative" "3") (const_int 16)
|
||||
|
|
@ -192,7 +192,7 @@
|
|||
gcc_unreachable ();
|
||||
}
|
||||
"
|
||||
[(set_attr "type" "*,*,*,*,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
|
||||
[(set_attr "type" "multiple,multiple,multiple,multiple,load2,load2,store2,f_mcrr,f_mrrc,ffarithd,f_loadd,f_stored")
|
||||
(set (attr "length") (cond [(eq_attr "alternative" "1") (const_int 8)
|
||||
(eq_attr "alternative" "2") (const_int 12)
|
||||
(eq_attr "alternative" "3") (const_int 16)
|
||||
|
|
@ -261,7 +261,7 @@
|
|||
"
|
||||
[(set_attr "conds" "unconditional")
|
||||
(set_attr "type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,\
|
||||
load1,store1,fcpys,*,f_mcr,f_mrc,*")
|
||||
load1,store1,fcpys,mov_reg,f_mcr,f_mrc,multiple")
|
||||
(set_attr "length" "4,4,4,4,4,4,4,4,8")]
|
||||
)
|
||||
|
||||
|
|
@ -311,7 +311,7 @@
|
|||
}
|
||||
"
|
||||
[(set_attr "conds" "unconditional")
|
||||
(set_attr "type" "load1,store1,fcpys,*,f_mcr,f_mrc,*")
|
||||
(set_attr "type" "load1,store1,fcpys,mov_reg,f_mcr,f_mrc,multiple")
|
||||
(set_attr "length" "4,4,4,4,4,4,8")]
|
||||
)
|
||||
|
||||
|
|
@ -429,7 +429,7 @@
|
|||
}
|
||||
"
|
||||
[(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,f_stored,\
|
||||
load2,store2,ffarithd,*")
|
||||
load2,store2,ffarithd,multiple")
|
||||
(set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
|
||||
(eq_attr "alternative" "7")
|
||||
(if_then_else
|
||||
|
|
@ -474,7 +474,7 @@
|
|||
}
|
||||
"
|
||||
[(set_attr "type" "f_mcrr,f_mrrc,fconstd,f_loadd,\
|
||||
f_stored,load2,store2,ffarithd,*")
|
||||
f_stored,load2,store2,ffarithd,multiple")
|
||||
(set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
|
||||
(eq_attr "alternative" "7")
|
||||
(if_then_else
|
||||
|
|
@ -578,7 +578,7 @@
|
|||
ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
|
||||
[(set_attr "conds" "use")
|
||||
(set_attr "length" "6,6,10,6,6,10,6,6,10")
|
||||
(set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcr,f_mrrc,f_mrrc,f_mrrc")]
|
||||
(set_attr "type" "ffarithd,ffarithd,ffarithd,f_mcr,f_mcr,f_mcrr,f_mrrc,f_mrrc,f_mrrc")]
|
||||
)
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue