Add basic armv8-a support
2012-10-17 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* config/arm/lib1funcs.S (__ARM_ARCH__): Define for ARMv8-A.
2012-10-17 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
* gcc.target/arm/ftest-armv8a-arm.c: New testcase.
* gcc.target/arm/ftest-armv8a-thumb.c: Likewise.
* gcc.target/arm/ftest-support-arm.h (feature_matrix): Add
ARMv8-A row.
* gcc.target/arm/ftest-support-thumb.h (feature_matrix):
Likewise.
* gcc.target/arm/ftest-support.h (architecture): Add ARMv8-A.
* lib/target-supports.exp: Add ARMv8-A architecture expectation.
2012-10-17 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config.gcc: Add support for ARMv8 for arm*-*-* targets.
* config/arm/arm-arches.def: Add armv8-a
* config/arm/arm-fpus.def: Add fp-armv8, neon-fp-armv8,
crypto-neon-fp-armv8. Add crypto field.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm.c (FL_FOR_ARCH8A): Likewise.
(arm_arch8): New global variable.
(ARM_FPU): Add crypto parameter.
(arm_option_override): Set arm_arch8, update comments.
* config/arm/arm.h (TARGET_CRYPTO): New macro.
(arm_fpu_desc): Add crypto field.
(base_architecture): Add ARMv8 entry.
(arm_arch8): New variable declaration.
* config/arm/bpabi.h: ARMv8 supports BE8.
* doc/invoke.texi: Document ARMv8 options.
Co-Authored-By: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
From-SVN: r192558
This commit is contained in:
Matthew Gretton-Dann
Ramana Radhakrishnan
parent
a9ba8ba56c
commit
595fefee5d
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@ -1,3 +1,22 @@
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2012-10-17 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
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* config.gcc: Add support for ARMv8 for arm*-*-* targets.
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* config/arm/arm-arches.def: Add armv8-a
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* config/arm/arm-fpus.def: Add fp-armv8, neon-fp-armv8,
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crypto-neon-fp-armv8. Add crypto field.
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* config/arm/arm-tables.opt: Regenerate.
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* config/arm/arm.c (FL_FOR_ARCH8A): Likewise.
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(arm_arch8): New global variable.
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(ARM_FPU): Add crypto parameter.
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(arm_option_override): Set arm_arch8, update comments.
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* config/arm/arm.h (TARGET_CRYPTO): New macro.
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(arm_fpu_desc): Add crypto field.
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(base_architecture): Add ARMv8 entry.
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(arm_arch8): New variable declaration.
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* config/arm/bpabi.h: ARMv8 supports BE8.
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* doc/invoke.texi: Document ARMv8 options.
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2012-10-17 Aldy Hernandez <aldyh@redhat.com>
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PR middle-end/54893
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@ -3040,7 +3040,7 @@ case "${target}" in
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"" \
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| armv[23456] | armv2a | armv3m | armv4t | armv5t \
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| armv5te | armv6j |armv6k | armv6z | armv6zk | armv6-m \
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| armv7 | armv7-a | armv7-r | armv7-m \
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| armv7 | armv7-a | armv7-r | armv7-m | armv8-a \
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| iwmmxt | ep9312)
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# OK
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;;
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@ -3066,7 +3066,8 @@ case "${target}" in
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| vfp | vfp3 | vfpv3 \
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| vfpv3-fp16 | vfpv3-d16 | vfpv3-d16-fp16 | vfpv3xd \
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| vfpv3xd-fp16 | neon | neon-fp16 | vfpv4 | vfpv4-d16 \
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| fpv4-sp-d16 | neon-vfpv4)
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| fpv4-sp-d16 | neon-vfpv4 | fp-arm-v8 | neon-fp-armv8 \
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| crypto-neon-fp-armv8)
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# OK
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;;
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*)
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@ -55,5 +55,6 @@ ARM_ARCH("armv7-a", cortexa8, 7A, FL_CO_PROC | FL_FOR_ARCH7A)
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ARM_ARCH("armv7-r", cortexr4, 7R, FL_CO_PROC | FL_FOR_ARCH7R)
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ARM_ARCH("armv7-m", cortexm3, 7M, FL_CO_PROC | FL_FOR_ARCH7M)
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ARM_ARCH("armv7e-m", cortexm4, 7EM, FL_CO_PROC | FL_FOR_ARCH7EM)
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ARM_ARCH("armv8-a", cortexa15, 8A, FL_CO_PROC | FL_FOR_ARCH8A)
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ARM_ARCH("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT)
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ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2)
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@ -21,24 +21,28 @@
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/* Before using #include to read this file, define a macro:
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ARM_FPU(NAME, MODEL, REV, VFP_REGS, NEON, FP16)
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ARM_FPU(NAME, MODEL, REV, VFP_REGS, NEON, FP16, CRYPTO)
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The arguments are the fields of struct arm_fpu_desc.
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genopt.sh assumes no whitespace up to the first "," in each entry. */
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ARM_FPU("vfp", ARM_FP_MODEL_VFP, 2, VFP_REG_D16, false, false)
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ARM_FPU("vfpv3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false)
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ARM_FPU("vfpv3-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, true)
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ARM_FPU("vfpv3-d16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, false)
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ARM_FPU("vfpv3-d16-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, true)
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ARM_FPU("vfpv3xd", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, false)
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ARM_FPU("vfpv3xd-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, true)
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ARM_FPU("neon", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true , false)
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ARM_FPU("neon-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true, true)
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ARM_FPU("vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, false, true)
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ARM_FPU("vfpv4-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_D16, false, true)
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ARM_FPU("fpv4-sp-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, false, true)
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ARM_FPU("neon-vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, true, true)
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ARM_FPU("vfp", ARM_FP_MODEL_VFP, 2, VFP_REG_D16, false, false, false)
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ARM_FPU("vfpv3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false, false)
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ARM_FPU("vfpv3-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, true, false)
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ARM_FPU("vfpv3-d16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, false, false)
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ARM_FPU("vfpv3-d16-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, true, false)
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ARM_FPU("vfpv3xd", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, false, false)
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ARM_FPU("vfpv3xd-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, true, false)
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ARM_FPU("neon", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true , false, false)
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ARM_FPU("neon-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true, true, false)
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ARM_FPU("vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, false, true, false)
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ARM_FPU("vfpv4-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_D16, false, true, false)
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ARM_FPU("fpv4-sp-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, false, true, false)
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ARM_FPU("neon-vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, true, true, false)
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ARM_FPU("fp-armv8", ARM_FP_MODEL_VFP, 8, VFP_REG_D32, false, true, false)
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ARM_FPU("neon-fp-armv8",ARM_FP_MODEL_VFP, 8, VFP_REG_D32, true, true, false)
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ARM_FPU("crypto-neon-fp-armv8",
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ARM_FP_MODEL_VFP, 8, VFP_REG_D32, true, true, true)
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/* Compatibility aliases. */
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ARM_FPU("vfp3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false)
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ARM_FPU("vfp3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false, false)
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@ -347,10 +347,13 @@ EnumValue
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Enum(arm_arch) String(armv7e-m) Value(22)
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EnumValue
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Enum(arm_arch) String(iwmmxt) Value(23)
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Enum(arm_arch) String(armv8-a) Value(23)
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EnumValue
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Enum(arm_arch) String(iwmmxt2) Value(24)
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Enum(arm_arch) String(iwmmxt) Value(24)
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EnumValue
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Enum(arm_arch) String(iwmmxt2) Value(25)
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Enum
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Name(arm_fpu) Type(int)
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@ -396,5 +399,14 @@ EnumValue
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Enum(arm_fpu) String(neon-vfpv4) Value(12)
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EnumValue
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Enum(arm_fpu) String(vfp3) Value(13)
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Enum(arm_fpu) String(fp-armv8) Value(13)
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EnumValue
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Enum(arm_fpu) String(neon-fp-armv8) Value(14)
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EnumValue
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Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(15)
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EnumValue
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Enum(arm_fpu) String(vfp3) Value(16)
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@ -686,6 +686,7 @@ static int thumb_call_reg_needed;
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architecture. */
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#define FL_ARCH7 (1 << 22) /* Architecture 7. */
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#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */
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#define FL_ARCH8 (1 << 24) /* Architecture 8. */
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#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
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#define FL_IWMMXT2 (1 << 30) /* "Intel Wireless MMX2 technology". */
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@ -716,6 +717,8 @@ static int thumb_call_reg_needed;
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#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
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#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
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#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
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#define FL_FOR_ARCH8A (FL_FOR_ARCH7 | FL_ARCH6K | FL_ARCH8 | FL_THUMB_DIV \
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| FL_ARM_DIV | FL_NOTM)
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/* The bits in this mask specify which
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instructions we are allowed to generate. */
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@ -765,6 +768,9 @@ int arm_arch_notm = 0;
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/* Nonzero if instructions present in ARMv7E-M can be used. */
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int arm_arch7em = 0;
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/* Nonzero if instructions present in ARMv8 can be used. */
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int arm_arch8 = 0;
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/* Nonzero if this chip can benefit from load scheduling. */
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int arm_ld_sched = 0;
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@ -1059,8 +1065,8 @@ char arm_arch_name[] = "__ARM_ARCH_0UNK__";
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static const struct arm_fpu_desc all_fpus[] =
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{
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#define ARM_FPU(NAME, MODEL, REV, VFP_REGS, NEON, FP16) \
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{ NAME, MODEL, REV, VFP_REGS, NEON, FP16 },
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#define ARM_FPU(NAME, MODEL, REV, VFP_REGS, NEON, FP16, CRYPTO) \
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{ NAME, MODEL, REV, VFP_REGS, NEON, FP16, CRYPTO },
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#include "arm-fpus.def"
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#undef ARM_FPU
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};
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@ -1743,6 +1749,7 @@ arm_option_override (void)
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arm_arch6m = arm_arch6 && !arm_arch_notm;
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arm_arch7 = (insn_flags & FL_ARCH7) != 0;
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arm_arch7em = (insn_flags & FL_ARCH7EM) != 0;
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arm_arch8 = (insn_flags & FL_ARCH8) != 0;
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arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
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arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
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@ -1959,6 +1966,7 @@ arm_option_override (void)
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/* Enable -munaligned-access by default for
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- all ARMv6 architecture-based processors
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- ARMv7-A, ARMv7-R, and ARMv7-M architecture-based processors.
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- ARMv8 architecture-base processors.
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Disable -munaligned-access by default for
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- all pre-ARMv6 architecture-based processors
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@ -296,6 +296,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
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/* FPU supports fused-multiply-add operations. */
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#define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4)
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/* FPU supports Crypto extensions. */
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#define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto)
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/* FPU supports Neon instructions. The setting of this macro gets
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revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
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and TARGET_HARD_FLOAT to ensure that NEON instructions are
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@ -400,6 +403,7 @@ extern const struct arm_fpu_desc
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enum vfp_reg_type regs;
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int neon;
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int fp16;
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int crypto;
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} *arm_fpu_desc;
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/* Which floating point hardware to schedule for. */
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@ -443,7 +447,8 @@ enum base_architecture
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BASE_ARCH_7A = 7,
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BASE_ARCH_7R = 7,
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BASE_ARCH_7M = 7,
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BASE_ARCH_7EM = 7
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BASE_ARCH_7EM = 7,
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BASE_ARCH_8A = 8
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};
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/* The major revision number of the ARM Architecture implemented by the target. */
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@ -482,6 +487,9 @@ extern int arm_arch_notm;
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/* Nonzero if instructions present in ARMv7E-M can be used. */
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extern int arm_arch7em;
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/* Nonzero if this chip supports the ARM Architecture 8 extensions. */
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extern int arm_arch8;
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/* Nonzero if this chip can benefit from load scheduling. */
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extern int arm_ld_sched;
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@ -64,6 +64,7 @@
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|march=armv7-m|mcpu=cortex-m3 \
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|march=armv7e-m|mcpu=cortex-m4 \
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|march=armv6-m|mcpu=cortex-m0 \
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|march=armv8-a \
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:%{!r:--be8}}}"
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#else
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#define BE8_LINK_SPEC \
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@ -74,6 +75,7 @@
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|march=armv7-m|mcpu=cortex-m3 \
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|march=armv7e-m|mcpu=cortex-m4 \
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|march=armv6-m|mcpu=cortex-m0 \
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|march=armv8-a \
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:%{!r:--be8}}}"
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#endif
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@ -972,6 +972,38 @@
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@subsubsection Fused-multiply-accumulate
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@itemize @bullet
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@item float32x2_t vfma_f32 (float32x2_t, float32x2_t, float32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vfma.f32 @var{d0}, @var{d0}, @var{d0}}
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@end itemize
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@itemize @bullet
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@item float32x4_t vfmaq_f32 (float32x4_t, float32x4_t, float32x4_t)
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@*@emph{Form of expected instruction(s):} @code{vfma.f32 @var{q0}, @var{q0}, @var{q0}}
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@end itemize
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@subsubsection Fused-multiply-subtract
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@itemize @bullet
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@item float32x2_t vfms_f32 (float32x2_t, float32x2_t, float32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vfms.f32 @var{d0}, @var{d0}, @var{d0}}
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@end itemize
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@itemize @bullet
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@item float32x4_t vfmsq_f32 (float32x4_t, float32x4_t, float32x4_t)
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@*@emph{Form of expected instruction(s):} @code{vfms.f32 @var{q0}, @var{q0}, @var{q0}}
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@end itemize
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@subsubsection Subtraction
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@itemize @bullet
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@ -1496,24 +1528,6 @@
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@subsubsection Comparison (greater-than-or-equal-to)
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@itemize @bullet
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@item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
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@end itemize
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@itemize @bullet
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@item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t)
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@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
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@end itemize
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@itemize @bullet
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@item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t)
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@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
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@end itemize
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@itemize @bullet
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@item uint32x2_t vcge_s32 (int32x2_t, int32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
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@ -1539,20 +1553,20 @@
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@itemize @bullet
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@item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t)
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@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
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@item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t)
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@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
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@end itemize
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@itemize @bullet
|
||||
@item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
|
||||
@item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
|
||||
@item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
|
|
@ -1580,28 +1594,28 @@
|
|||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
|
||||
|
||||
@subsubsection Comparison (less-than-or-equal-to)
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x2_t vcle_s32 (int32x2_t, int32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
|
||||
|
|
@ -1627,20 +1641,20 @@
|
|||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
|
||||
@item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
|
||||
@item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
|
||||
@item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
|
|
@ -1668,28 +1682,28 @@
|
|||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
|
||||
|
||||
@subsubsection Comparison (greater-than)
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x2_t vcgt_s32 (int32x2_t, int32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
|
||||
|
|
@ -1715,20 +1729,20 @@
|
|||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
|
||||
@item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
|
||||
@item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
|
||||
@item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
|
|
@ -1756,28 +1770,28 @@
|
|||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
|
||||
|
||||
@subsubsection Comparison (less-than)
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x2_t vclt_s32 (int32x2_t, int32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
|
||||
|
|
@ -1803,20 +1817,20 @@
|
|||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
|
||||
@item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
|
||||
@item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
|
||||
@item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
|
|
@ -1844,6 +1858,24 @@
|
|||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t)
|
||||
@*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
|
||||
|
||||
@subsubsection Comparison (absolute greater-than-or-equal-to)
|
||||
|
|
@ -4810,13 +4842,13 @@
|
|||
|
||||
@itemize @bullet
|
||||
@item uint64_t vgetq_lane_u64 (uint64x2_t, const int)
|
||||
@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
|
||||
@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} @emph{or} @code{fmrrd @var{r0}, @var{r0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
@itemize @bullet
|
||||
@item int64_t vgetq_lane_s64 (int64x2_t, const int)
|
||||
@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
|
||||
@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} @emph{or} @code{fmrrd @var{r0}, @var{r0}, @var{d0}}
|
||||
@end itemize
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -11004,6 +11004,7 @@ of the @option{-mcpu=} option. Permissible names are: @samp{armv2},
|
|||
@samp{armv6}, @samp{armv6j},
|
||||
@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, @samp{armv6-m},
|
||||
@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m},
|
||||
@samp{armv8-a},
|
||||
@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}.
|
||||
|
||||
@option{-march=native} causes the compiler to auto-detect the architecture
|
||||
|
|
@ -11017,7 +11018,8 @@ This specifies what floating-point hardware (or hardware emulation) is
|
|||
available on the target. Permissible names are: @samp{vfp}, @samp{vfpv3},
|
||||
@samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd},
|
||||
@samp{vfpv3xd-fp16}, @samp{neon}, @samp{neon-fp16}, @samp{vfpv4},
|
||||
@samp{vfpv4-d16}, @samp{fpv4-sp-d16} and @samp{neon-vfpv4}.
|
||||
@samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4},
|
||||
@samp{fp-armv8}, @samp{neon-fp-armv8}, and @samp{crypto-neon-fp-armv8}.
|
||||
|
||||
If @option{-msoft-float} is specified this specifies the format of
|
||||
floating-point values.
|
||||
|
|
|
|||
|
|
@ -1,3 +1,14 @@
|
|||
2012-10-17 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* gcc.target/arm/ftest-armv8a-arm.c: New testcase.
|
||||
* gcc.target/arm/ftest-armv8a-thumb.c: Likewise.
|
||||
* gcc.target/arm/ftest-support-arm.h (feature_matrix): Add
|
||||
ARMv8-A row.
|
||||
* gcc.target/arm/ftest-support-thumb.h (feature_matrix):
|
||||
Likewise.
|
||||
* gcc.target/arm/ftest-support.h (architecture): Add ARMv8-A.
|
||||
* lib/target-supports.exp: Add ARMv8-A architecture expectation.
|
||||
|
||||
2012-10-16 Jan Hubicka <jh@suse.cz>
|
||||
|
||||
* gcc.target/i386/l_fma_float_?.c: Update.
|
||||
|
|
|
|||
|
|
@ -0,0 +1,14 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target arm_nothumb } */
|
||||
/* { dg-require-effective-target arm_arch_v8a_multilib } */
|
||||
/* { dg-options "-marm" } */
|
||||
/* { dg-add-options arm_arch_v8a } */
|
||||
|
||||
#include "ftest-support-arm.h"
|
||||
|
||||
int
|
||||
main (void)
|
||||
{
|
||||
return ftest (ARCH_V8A);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/* { dg-do run } */
|
||||
/* { dg-require-effective-target arm_eabi } */
|
||||
/* { dg-require-effective-target arm_arch_v8a_multilib } */
|
||||
/* { dg-options "-mthumb" } */
|
||||
/* { dg-add-options arm_arch_v8a } */
|
||||
|
||||
#include "ftest-support-thumb.h"
|
||||
|
||||
int
|
||||
main (void)
|
||||
{
|
||||
return ftest (ARCH_V8A);
|
||||
}
|
||||
|
||||
|
|
@ -26,4 +26,5 @@ int feature_matrix[ARCH_COUNT][NUM_FEATURES] =
|
|||
{7, 1, 2, 'A', 1, 15, 1, 1, 1, 1, 1}, /* ARCH_V7A. */
|
||||
{7, 1, 2, 'R', 1, 15, 1, 1, 1, 1, 1}, /* ARCH_V7R. */
|
||||
{7, 0, 2, 'M', 1, 7, 1, 0, 0, 1, 1}, /* ARCH_V7M. */
|
||||
{7, 0, 2, 'M', 1, 7, 1, 1, 0, 1, 1}}; /* ARCH_V7EM. */
|
||||
{7, 0, 2, 'M', 1, 7, 1, 1, 0, 1, 1}, /* ARCH_V7EM. */
|
||||
{8, 1, 2, 'A', 1, 15, 1, 1, 1, 1, 1}}; /* ARCH_V8A. */
|
||||
|
|
|
|||
|
|
@ -26,4 +26,5 @@ int feature_matrix[ARCH_COUNT][NUM_FEATURES] =
|
|||
{7, 1, 2, 'A', 1, 15, 1, 1, 1, 1, 1}, /* ARCH_V7A. */
|
||||
{7, 1, 2, 'R', 1, 15, 1, 1, 1, 1, 1}, /* ARCH_V7R. */
|
||||
{7, 0, 2, 'M', 1, 7, 1, 0, 0, 1, 1}, /* ARCH_V7M. */
|
||||
{7, 0, 2, 'M', 1, 7, 1, 1, 1, 1, 1}}; /* ARCH_V7EM. */
|
||||
{7, 0, 2, 'M', 1, 7, 1, 1, 1, 1, 1}, /* ARCH_V7EM. */
|
||||
{8, 1, 2, 'A', 1, 15, 1, 1, 1, 1, 1}}; /* ARCH_V8A. */
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@ enum architecture {
|
|||
ARCH_V7R,
|
||||
ARCH_V7M,
|
||||
ARCH_V7EM,
|
||||
ARCH_V8A,
|
||||
ARCH_COUNT
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -2246,7 +2246,8 @@ foreach { armfunc armflag armdef } { v4 "-march=armv4 -marm" __ARM_ARCH_4__
|
|||
v7a "-march=armv7-a" __ARM_ARCH_7A__
|
||||
v7r "-march=armv7-r" __ARM_ARCH_7R__
|
||||
v7m "-march=armv7-m -mthumb" __ARM_ARCH_7M__
|
||||
v7em "-march=armv7e-m -mthumb" __ARM_ARCH_7EM__ } {
|
||||
v7em "-march=armv7e-m -mthumb" __ARM_ARCH_7EM__
|
||||
v8a "-march=armv8-a" __ARM_ARCH_8A__ } {
|
||||
eval [string map [list FUNC $armfunc FLAG $armflag DEF $armdef ] {
|
||||
proc check_effective_target_arm_arch_FUNC_ok { } {
|
||||
if { [ string match "*-marm*" "FLAG" ] &&
|
||||
|
|
|
|||
|
|
@ -1,3 +1,7 @@
|
|||
2012-10-17 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
|
||||
|
||||
* config/arm/lib1funcs.S (__ARM_ARCH__): Define for ARMv8-A.
|
||||
|
||||
2012-10-15 Matthias Klose <doko@ubuntu.com>
|
||||
|
||||
* config.host: Match arm*-*-linux-* for ARM Linux/GNU.
|
||||
|
|
|
|||
|
|
@ -109,6 +109,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
|||
# define __ARM_ARCH__ 7
|
||||
#endif
|
||||
|
||||
#if defined(__ARM_ARCH_8A__)
|
||||
# define __ARM_ARCH__ 8
|
||||
#endif
|
||||
|
||||
#ifndef __ARM_ARCH__
|
||||
#error Unable to determine architecture.
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue