(FUNCTION_INCOMING_ARG): Delete definition.
(RTX_COSTS) [PLUS]: Rewrite. (output_scc_insn): Delete. (output_floatsisf2): Delete. (output_floatsidf2): Delete. (PREDICATE_CODES): Define, but leave within #if 0 for now. (CONDITIONAL_REGISTER_USAGE): Never make PIC_OFFSET_TABLE_REGNUM fixed. (INITIALIZE_PIC): Delete. From-SVN: r6293
This commit is contained in:
Torbjorn Granlund
parent
23f6f34fca
commit
5a1c10de98
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@ -42,7 +42,7 @@ extern int target_flags;
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/* Disable all FP registers (they all become fixed). This may be necessary
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for compiling kernels which perform lazy context switching of FP regs.
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Note if you use this option and try to perform floating point operations
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Note if you use this option and try to perform floating point operations
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the compiler will abort! */
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#define TARGET_DISABLE_FPREGS (target_flags & 2)
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@ -53,7 +53,7 @@ extern int target_flags;
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/* Force all function calls to indirect addressing via a register. This
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avoids lossage when the function is very far away from the current PC.
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??? What about simple jumps, they can suffer from the same problem.
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??? What about simple jumps, they can suffer from the same problem.
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Would require significant surgery in pa.md. */
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#define TARGET_LONG_CALLS (target_flags & 16)
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@ -64,7 +64,7 @@ extern int target_flags;
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/* Emit directives only understood by GAS. This allows parameter
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relocations to work for static functions. There is no way
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to make them work the HP assembler at this time.
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to make them work the HP assembler at this time.
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Also forces a colon to be tacked onto the end of local and
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global labes. */
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@ -115,7 +115,7 @@ extern int target_flags;
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/* Defines for a K&R CC */
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#define CC1_SPEC "%{pg:} %{p:}"
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#define LINK_SPEC "-u main"
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/* Allow $ in identifiers. */
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@ -144,7 +144,7 @@ extern int target_flags;
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}
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/* Omit frame pointer at high optimization levels. */
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#define OPTIMIZATION_OPTIONS(OPTIMIZE) \
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{ \
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if (OPTIMIZE >= 2) \
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@ -244,9 +244,9 @@ extern int target_flags;
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HP-PA 1.0 has 32 fullword registers and 16 floating point
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registers. The floating point registers hold either word or double
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word values.
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16 additional registers are reserved.
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HP-PA 1.1 has 32 fullword registers and 32 floating point
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registers. However, the floating point registers behave
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differently: the left and right halves of registers are addressable
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@ -291,7 +291,6 @@ extern int target_flags;
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Freg 8L-11R = Temporary Registers
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Freg 12L-21R = Preserved Registers
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Freg 22L-31R = Temporary Registers
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*/
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@ -335,7 +334,7 @@ extern int target_flags;
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0, 0, 0, 0, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, \
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1, 1, 1, 1, 1, 1, 1, 1, \
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1}
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1}
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/* Make sure everything's fine if we *don't* have a given processor.
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This assumes that putting a register in fixed_regs will keep the
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@ -371,8 +370,10 @@ extern int target_flags;
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if (TEST_HARD_REG_BIT (x, i)) \
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fixed_regs[i] = call_used_regs[i] = 1; \
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} \
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/* This makes cse think PIC_OFFSET_TABLE_REGNUM is not clobbered
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in calls. \
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if (flag_pic) \
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fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
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fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; */ \
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}
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/* Allocated the call used registers first. This should minimize
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@ -452,7 +453,7 @@ extern int target_flags;
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/* Value should be nonzero if functions must have frame pointers. */
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#define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
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/* C statement to store the difference between the frame pointer
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and the stack pointer values immediately after the function prologue.
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@ -475,7 +476,6 @@ extern int target_flags;
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#define PIC_OFFSET_TABLE_REGNUM 19
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#define INITIALIZE_PIC initialize_pic ()
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#define FINALIZE_PIC finalize_pic ()
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/* SOM ABI says that objects larger than 64 bits are returned in memory. */
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@ -515,7 +515,7 @@ extern int target_flags;
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enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FP_REGS, GENERAL_OR_FP_REGS,
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HI_SNAKE_FP_REGS, SNAKE_FP_REGS, GENERAL_OR_SNAKE_FP_REGS,
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FP_OR_SNAKE_FP_REGS, NON_SHIFT_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
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FP_OR_SNAKE_FP_REGS, NON_SHIFT_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
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#define N_REG_CLASSES (int) LIM_REG_CLASSES
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@ -567,7 +567,7 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FP_REGS, GENERAL_OR_FP_REGS,
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(CLASS == FP_REGS || CLASS == SNAKE_FP_REGS || CLASS == HI_SNAKE_FP_REGS)
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/* Get reg_class from a letter such as appears in the machine description.
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Note 'Z' is not the same as 'r' since SHIFT_REGS is not part of
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Note 'Z' is not the same as 'r' since SHIFT_REGS is not part of
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GENERAL_REGS. */
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#define REG_CLASS_FROM_LETTER(C) \
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@ -628,7 +628,7 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FP_REGS, GENERAL_OR_FP_REGS,
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#define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
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secondary_reload_class (CLASS, MODE, IN)
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/* On the PA it is not possible to directly move data between
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/* On the PA it is not possible to directly move data between
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GENERAL_REGS and FP_REGS. */
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#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
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((FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2)) \
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@ -678,12 +678,12 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FP_REGS, GENERAL_OR_FP_REGS,
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??? Have to check on this.*/
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#define FIRST_PARM_OFFSET(FNDECL) -32
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#define FIRST_PARM_OFFSET(FNDECL) -32
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/* Absolute value of offset from top-of-stack address to location to store the
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function parameter if it can't go in a register.
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Addresses for following parameters are computed relative to this one. */
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#define FIRST_PARM_CALLER_OFFSET(FNDECL) -32
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#define FIRST_PARM_CALLER_OFFSET(FNDECL) -32
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/* When a parameter is passed in a register, stack space is still
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@ -699,11 +699,11 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FP_REGS, GENERAL_OR_FP_REGS,
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doesn't behave itself when the stack pointer moves within
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the function! */
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#define ACCUMULATE_OUTGOING_ARGS
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/* The weird HPPA calling conventions require a minimum of 48 bytes on
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/* The weird HPPA calling conventions require a minimum of 48 bytes on
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the stack: 16 bytes for register saves, and 32 bytes for magic.
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This is the difference between the logical top of stack and the
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actual sp. */
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actual sp. */
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#define STACK_POINTER_OFFSET -32
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#define STACK_DYNAMIC_OFFSET(FNDECL) \
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@ -726,7 +726,7 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FP_REGS, GENERAL_OR_FP_REGS,
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#define FUNCTION_VALUE(VALTYPE, FUNC) \
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gen_rtx (REG, TYPE_MODE (VALTYPE), ((TYPE_MODE (VALTYPE) == SFmode ||\
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gen_rtx (REG, TYPE_MODE (VALTYPE), ((TYPE_MODE (VALTYPE) == SFmode || \
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TYPE_MODE (VALTYPE) == DFmode) ? \
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(TARGET_SNAKE ? 44 : 32) : 28))
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@ -823,12 +823,6 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FP_REGS, GENERAL_OR_FP_REGS,
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: (27 - (CUM) - FUNCTION_ARG_SIZE ((MODE), (TYPE))))))\
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: 0)
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/* Define where a function finds its arguments.
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This would be different from FUNCTION_ARG if we had register windows. */
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#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
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FUNCTION_ARG (CUM, MODE, TYPE, NAMED)
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/* For an arg passed partly in registers and partly in memory,
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this is the number of registers used.
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For args passed entirely in registers or entirely in memory, zero. */
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@ -1002,9 +996,9 @@ extern union tree_node *current_function_decl;
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This code template is copied from text segment to stack location
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and then patched with INITIALIZE_TRAMPOLINE to contain
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valid values, and then entered as a subroutine.
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valid values, and then entered as a subroutine.
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It is best to keep this as small as possible to avoid having to
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It is best to keep this as small as possible to avoid having to
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flush multiple lines in the cache. */
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#define TRAMPOLINE_TEMPLATE(FILE) \
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@ -1026,7 +1020,7 @@ extern union tree_node *current_function_decl;
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Flush the cache entries corresponding to the first and last addresses
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of the trampoline. This is necessary as the trampoline may cross two
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cache lines.
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cache lines.
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If the code part of the trampoline ever grows to > 32 bytes, then it
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will become necessary to hack on the cacheflush pattern in pa.md. */
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@ -1126,7 +1120,7 @@ extern union tree_node *current_function_decl;
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(GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
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|| (X) == CONST0_RTX (GET_MODE (X)))
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/* Subroutine for EXTRA_CONSTRAINT.
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/* Subroutine for EXTRA_CONSTRAINT.
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Return 1 iff OP is a pseudo which did not get a hard register and
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we are running the reload pass. */
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@ -1146,7 +1140,7 @@ extern union tree_node *current_function_decl;
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constrain_operands to fail.
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Also note `Q' accepts any memory operand during the reload pass.
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This includes out-of-range displacements in reg+d addressing.
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This includes out-of-range displacements in reg+d addressing.
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This makes for better code. (??? For 2.5 address this issue).
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`R' is unused.
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@ -1352,7 +1346,7 @@ do \
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} \
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} \
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while (0)
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/* Store the user-specified part of SYMBOL_NAME in VAR.
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This is sort of inverse to ENCODE_SECTION_INFO. */
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@ -1437,7 +1431,7 @@ while (0)
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is a byte address (for indexing purposes)
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so give the MEM rtx a byte's mode. */
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#define FUNCTION_MODE SImode
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/* Define this if addresses of constant functions
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shouldn't be put through pseudo regs where they can be cse'd.
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Desirable on machines where ordinary constants are expensive
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@ -1483,7 +1477,7 @@ while (0)
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Make moves from SAR so expensive they should never happen. We used to
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have 0xffff here, but that generates overflow in rare cases.
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Copies involving a FP register and a non-FP register are relatively
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Copies involving a FP register and a non-FP register are relatively
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expensive because they must go through memory.
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Other copies are reasonably cheap. */
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@ -1498,17 +1492,21 @@ while (0)
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switch on CODE. The purpose for the cost of MULT is to encourage
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`synth_mult' to find a synthetic multiply when reasonable. */
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#define RTX_COSTS(X,CODE,OUTER_CODE) \
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case MULT: \
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return TARGET_SNAKE && ! TARGET_DISABLE_FPREGS \
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? COSTS_N_INSNS (8) : COSTS_N_INSNS (20); \
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case DIV: \
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case UDIV: \
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case MOD: \
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case UMOD: \
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return COSTS_N_INSNS (60); \
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case PLUS: /* this includes shNadd insns */ \
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return COSTS_N_INSNS (1) + 2;
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#define RTX_COSTS(X,CODE,OUTER_CODE) \
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case MULT: \
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return TARGET_SNAKE && ! TARGET_DISABLE_FPREGS \
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? COSTS_N_INSNS (8) : COSTS_N_INSNS (20); \
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case DIV: \
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case UDIV: \
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case MOD: \
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case UMOD: \
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return COSTS_N_INSNS (60); \
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case PLUS: \
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if (GET_CODE (XEXP (X, 0)) == MULT \
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&& shadd_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \
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return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \
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+ rtx_cost (XEXP (X, 1), OUTER_CODE)); \
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break;
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/* Adjust the cost of dependencies. */
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@ -1531,8 +1529,8 @@ while (0)
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are expected to clobber their arguments, %r1, %r29, and %r31 and
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nothing else.
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These macros tell reorg that the references to arguments and
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register clobbers for millicode calls do not appear to happen
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These macros tell reorg that the references to arguments and
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register clobbers for millicode calls do not appear to happen
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until after the millicode call. This allows reorg to put insns
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which set the argument registers into the delay slot of the millicode
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call -- thus they act more like traditional CALL_INSNs.
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@ -1552,7 +1550,7 @@ while (0)
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&& GET_CODE (PATTERN (X)) != SEQUENCE \
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&& GET_CODE (PATTERN (X)) != USE \
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&& GET_CODE (PATTERN (X)) != CLOBBER \
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&& get_attr_type (X) == TYPE_MILLI))
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&& get_attr_type (X) == TYPE_MILLI))
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/* Control the assembler format that we output. */
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@ -1702,7 +1700,7 @@ readonly_data () \
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}\
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} while (0)
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/* The bogus HP assembler requires ALL external references to be
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/* The bogus HP assembler requires ALL external references to be
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"imported", even library calls. They look a bit different, so
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here's this macro. */
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@ -1790,7 +1788,7 @@ readonly_data () \
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output_ascii ((FILE), (P), (SIZE))
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#define ASM_OUTPUT_REG_PUSH(FILE,REGNO)
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#define ASM_OUTPUT_REG_POP(FILE,REGNO)
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#define ASM_OUTPUT_REG_POP(FILE,REGNO)
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/* This is how to output an element of a case-vector that is absolute.
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Note that this method makes filling these branch delay slots
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impossible. */
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@ -1928,15 +1926,12 @@ extern char *output_ior ();
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extern char *output_move_double ();
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extern char *output_fp_move_double ();
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extern char *output_block_move ();
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extern char *output_scc_insn ();
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extern char *output_cbranch ();
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extern char *output_bb ();
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extern char *output_dbra ();
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extern char *output_movb ();
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extern char *output_return ();
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extern char *output_call ();
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extern char *output_floatsisf2 ();
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extern char *output_floatsidf2 ();
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extern char *output_mul_insn ();
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extern char *output_div_insn ();
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extern char *output_mod_insn ();
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@ -1948,3 +1943,38 @@ extern struct rtx_def *gen_cmp_fp ();
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extern void hppa_encode_label ();
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extern struct rtx_def *hppa_save_pic_table_rtx;
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#if 0
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#define PREDICATE_CODES \
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{"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
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{"reg_or_cint_move_operand", {SUBREG, REG, CONST_INT}}, \
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{"arith_operand", {SUBREG, REG, CONST_INT}}, \
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{"arith32_operand", {SUBREG, REG, CONST_INT}}, \
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{"arith11_operand", {SUBREG, REG, CONST_INT}}, \
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{"arith5_operand", {SUBREG, REG, CONST_INT}}, \
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{"pre_cint_operand", {CONST_INT}}, \
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{"post_cint_operand", {CONST_INT}}, \
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{"int5_operand", {CONST_INT}}, \
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{"uint5_operand", {CONST_INT}}, \
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{"uint32_operand", {CONST_INT}}, \
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{"int11_operand", {CONST_INT}}, \
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{"and_operand", {SUBREG, REG, CONST_INT}}, \
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{"ior_operand", {CONST_INT}}, \
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{"lhs_lshift_operand", {SUBREG, REG, CONST_INT}}, \
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{"lhs_lshift_cint_operand", {CONST_INT}}, \
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{"plus_xor_ior_operator", {PLUS, XOR, IOR}}, \
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{"shadd_operand", {CONST_INT}}, \
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{"eq_neq_comparison_operator", {EQ, NE}}, \
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{"movb_comparison_operator", {EQ, NE, LT, GE}}, \
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{"pc_or_label_operand", {LABEL_REF, PC}}, \
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{"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
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{"reg_or_nonsymb_mem_operand", {REG, SUBREG, MEM}}, \
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{"move_operand", {REG, SUBREG, CONST_INT, MEM}}, \
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{"pic_operand", {REG, SUBREG, CONST_INT, SYMBOL_REF, LABEL_REF, \
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CONST, HIGH, PC}}, /* No clue */ \
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{"function_label_operand", {SYMBOL_REF}}, \
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{"reg_or_0_or_nonsymb_mem_operand", {REG, SUBREG, CONST_INT, MEM}}, \
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{"div_operand", {REG, CONST_INT}}, \
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{"call_operand_address", {LABEL_REF, SYMBOL_REF, CONST_INT, \
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CONST, HIGH}},
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#endif
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