arm.c (thumb2_emit_strd_push): Rewrite to use pre-decrement on initial store.
* arm.c (thumb2_emit_strd_push): Rewrite to use pre-decrement on initial store. * thumb2.md (thumb2_storewb_parisi): New pattern. From-SVN: r202279
This commit is contained in:
Richard Earnshaw
Richard Earnshaw
parent
5922847b1c
commit
5a200acb05
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@ -1,3 +1,9 @@
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2013-09-05 Richard Earnshaw <rearnsha@arm.com>
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* arm.c (thumb2_emit_strd_push): Rewrite to use pre-decrement on
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initial store.
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* thumb2.md (thumb2_storewb_parisi): New pattern.
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2013-09-05 Yufeng Zhang <yufeng.zhang@arm.com>
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2013-09-05 Yufeng Zhang <yufeng.zhang@arm.com>
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* config/aarch64/aarch64-option-extensions.def: Add
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* config/aarch64/aarch64-option-extensions.def: Add
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@ -16814,123 +16814,165 @@ arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
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}
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}
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}
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}
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/* Generate and emit a pattern that will be recognized as STRD pattern. If even
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/* Generate and emit a sequence of insns equivalent to PUSH, but using
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number of registers are being pushed, multiple STRD patterns are created for
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STR and STRD. If an even number of registers are being pushed, one
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all register pairs. If odd number of registers are pushed, emit a
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or more STRD patterns are created for each register pair. If an
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combination of STRDs and STR for the prologue saves. */
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odd number of registers are pushed, emit an initial STR followed by
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as many STRD instructions as are needed. This works best when the
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stack is initially 64-bit aligned (the normal case), since it
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ensures that each STRD is also 64-bit aligned. */
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static void
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static void
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thumb2_emit_strd_push (unsigned long saved_regs_mask)
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thumb2_emit_strd_push (unsigned long saved_regs_mask)
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{
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{
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int num_regs = 0;
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int num_regs = 0;
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int i, j;
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int i;
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int regno;
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rtx par = NULL_RTX;
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rtx par = NULL_RTX;
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rtx insn = NULL_RTX;
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rtx dwarf = NULL_RTX;
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rtx dwarf = NULL_RTX;
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rtx tmp, reg, tmp1;
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rtx tmp;
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bool first = true;
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for (i = 0; i <= LAST_ARM_REGNUM; i++)
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num_regs = bit_count (saved_regs_mask);
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if (saved_regs_mask & (1 << i))
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num_regs++;
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gcc_assert (num_regs && num_regs <= 16);
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/* Pre-decrement the stack pointer, based on there being num_regs 4-byte
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registers to push. */
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tmp = gen_rtx_SET (VOIDmode,
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stack_pointer_rtx,
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plus_constant (Pmode, stack_pointer_rtx, -4 * num_regs));
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RTX_FRAME_RELATED_P (tmp) = 1;
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insn = emit_insn (tmp);
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/* Create sequence for DWARF info. */
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dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_regs + 1));
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/* RTLs cannot be shared, hence create new copy for dwarf. */
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tmp1 = gen_rtx_SET (VOIDmode,
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stack_pointer_rtx,
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plus_constant (Pmode, stack_pointer_rtx, -4 * num_regs));
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RTX_FRAME_RELATED_P (tmp1) = 1;
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XVECEXP (dwarf, 0, 0) = tmp1;
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/* Must be at least one register to save, and can't save SP or PC. */
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gcc_assert (num_regs > 0 && num_regs <= 14);
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gcc_assert (!(saved_regs_mask & (1 << SP_REGNUM)));
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gcc_assert (!(saved_regs_mask & (1 << SP_REGNUM)));
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gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM)));
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gcc_assert (!(saved_regs_mask & (1 << PC_REGNUM)));
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/* Var j iterates over all the registers to gather all the registers in
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/* Create sequence for DWARF info. All the frame-related data for
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saved_regs_mask. Var i gives index of register R_j in stack frame.
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debugging is held in this wrapper. */
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A PARALLEL RTX of register-pair is created here, so that pattern for
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dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_regs + 1));
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STRD can be matched. If num_regs is odd, 1st register will be pushed
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using STR and remaining registers will be pushed with STRD in pairs.
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If num_regs is even, all registers are pushed with STRD in pairs.
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Hence, skip first element for odd num_regs. */
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for (i = num_regs - 1, j = LAST_ARM_REGNUM; i >= (num_regs % 2); j--)
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if (saved_regs_mask & (1 << j))
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{
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/* Create RTX for store. New RTX is created for dwarf as
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they are not sharable. */
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reg = gen_rtx_REG (SImode, j);
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tmp = gen_rtx_SET (SImode,
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gen_frame_mem
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(SImode,
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plus_constant (Pmode, stack_pointer_rtx, 4 * i)),
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reg);
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tmp1 = gen_rtx_SET (SImode,
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/* Describe the stack adjustment. */
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gen_frame_mem
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tmp = gen_rtx_SET (VOIDmode,
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(SImode,
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stack_pointer_rtx,
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plus_constant (Pmode, stack_pointer_rtx, 4 * i)),
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plus_constant (Pmode, stack_pointer_rtx, -4 * num_regs));
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reg);
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RTX_FRAME_RELATED_P (tmp) = 1;
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RTX_FRAME_RELATED_P (tmp) = 1;
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XVECEXP (dwarf, 0, 0) = tmp;
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RTX_FRAME_RELATED_P (tmp1) = 1;
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if (((i - (num_regs % 2)) % 2) == 1)
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/* Find the first register. */
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/* When (i - (num_regs % 2)) is odd, the RTX to be emitted is yet to
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for (regno = 0; (saved_regs_mask & (1 << regno)) == 0; regno++)
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be created. Hence create it first. The STRD pattern we are
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;
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generating is :
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[ (SET (MEM (PLUS (SP) (NUM))) (reg_t1))
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(SET (MEM (PLUS (SP) (NUM + 4))) (reg_t2)) ]
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where the target registers need not be consecutive. */
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par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
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/* Register R_j is added in PARALLEL RTX. If (i - (num_regs % 2)) is
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i = 0;
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even, the reg_j is added as 0th element and if it is odd, reg_i is
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added as 1st element of STRD pattern shown above. */
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XVECEXP (par, 0, ((i - (num_regs % 2)) % 2)) = tmp;
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XVECEXP (dwarf, 0, (i + 1)) = tmp1;
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if (((i - (num_regs % 2)) % 2) == 0)
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/* If there's an odd number of registers to push. Start off by
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/* When (i - (num_regs % 2)) is even, RTXs for both the registers
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pushing a single register. This ensures that subsequent strd
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to be loaded are generated in above given STRD pattern, and the
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operations are dword aligned (assuming that SP was originally
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pattern can be emitted now. */
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64-bit aligned). */
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emit_insn (par);
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if ((num_regs & 1) != 0)
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i--;
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}
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if ((num_regs % 2) == 1)
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{
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{
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/* If odd number of registers are pushed, generate STR pattern to store
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rtx reg, mem, insn;
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lone register. */
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for (; (saved_regs_mask & (1 << j)) == 0; j--);
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tmp1 = gen_frame_mem (SImode, plus_constant (Pmode,
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reg = gen_rtx_REG (SImode, regno);
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stack_pointer_rtx, 4 * i));
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if (num_regs == 1)
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reg = gen_rtx_REG (SImode, j);
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mem = gen_frame_mem (Pmode, gen_rtx_PRE_DEC (Pmode,
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tmp = gen_rtx_SET (SImode, tmp1, reg);
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stack_pointer_rtx));
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else
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mem = gen_frame_mem (Pmode,
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gen_rtx_PRE_MODIFY
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(Pmode, stack_pointer_rtx,
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plus_constant (Pmode, stack_pointer_rtx,
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-4 * num_regs)));
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tmp = gen_rtx_SET (VOIDmode, mem, reg);
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RTX_FRAME_RELATED_P (tmp) = 1;
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RTX_FRAME_RELATED_P (tmp) = 1;
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insn = emit_insn (tmp);
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emit_insn (tmp);
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RTX_FRAME_RELATED_P (insn) = 1;
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add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
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tmp1 = gen_rtx_SET (SImode,
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tmp = gen_rtx_SET (VOIDmode, gen_frame_mem (Pmode, stack_pointer_rtx),
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gen_frame_mem
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reg);
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(SImode,
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RTX_FRAME_RELATED_P (tmp) = 1;
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plus_constant (Pmode, stack_pointer_rtx, 4 * i)),
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i++;
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reg);
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regno++;
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RTX_FRAME_RELATED_P (tmp1) = 1;
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XVECEXP (dwarf, 0, i) = tmp;
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XVECEXP (dwarf, 0, (i + 1)) = tmp1;
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first = false;
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}
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}
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add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
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while (i < num_regs)
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RTX_FRAME_RELATED_P (insn) = 1;
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if (saved_regs_mask & (1 << regno))
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{
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rtx reg1, reg2, mem1, mem2;
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rtx tmp0, tmp1, tmp2;
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int regno2;
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/* Find the register to pair with this one. */
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for (regno2 = regno + 1; (saved_regs_mask & (1 << regno2)) == 0;
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regno2++)
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;
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reg1 = gen_rtx_REG (SImode, regno);
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reg2 = gen_rtx_REG (SImode, regno2);
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if (first)
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{
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rtx insn;
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first = false;
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mem1 = gen_frame_mem (Pmode, plus_constant (Pmode,
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stack_pointer_rtx,
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-4 * num_regs));
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mem2 = gen_frame_mem (Pmode, plus_constant (Pmode,
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stack_pointer_rtx,
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-4 * (num_regs - 1)));
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tmp0 = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
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plus_constant (Pmode, stack_pointer_rtx,
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-4 * (num_regs)));
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tmp1 = gen_rtx_SET (VOIDmode, mem1, reg1);
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tmp2 = gen_rtx_SET (VOIDmode, mem2, reg2);
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RTX_FRAME_RELATED_P (tmp0) = 1;
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RTX_FRAME_RELATED_P (tmp1) = 1;
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RTX_FRAME_RELATED_P (tmp2) = 1;
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par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (3));
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XVECEXP (par, 0, 0) = tmp0;
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XVECEXP (par, 0, 1) = tmp1;
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XVECEXP (par, 0, 2) = tmp2;
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insn = emit_insn (par);
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RTX_FRAME_RELATED_P (insn) = 1;
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add_reg_note (insn, REG_FRAME_RELATED_EXPR, dwarf);
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}
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else
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{
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mem1 = gen_frame_mem (Pmode, plus_constant (Pmode,
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stack_pointer_rtx,
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4 * i));
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mem2 = gen_frame_mem (Pmode, plus_constant (Pmode,
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stack_pointer_rtx,
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4 * (i + 1)));
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tmp1 = gen_rtx_SET (VOIDmode, mem1, reg1);
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tmp2 = gen_rtx_SET (VOIDmode, mem2, reg2);
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RTX_FRAME_RELATED_P (tmp1) = 1;
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RTX_FRAME_RELATED_P (tmp2) = 1;
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par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
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XVECEXP (par, 0, 0) = tmp1;
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XVECEXP (par, 0, 1) = tmp2;
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emit_insn (par);
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}
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/* Create unwind information. This is an approximation. */
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tmp1 = gen_rtx_SET (VOIDmode,
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gen_frame_mem (Pmode,
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plus_constant (Pmode,
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stack_pointer_rtx,
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4 * i)),
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reg1);
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tmp2 = gen_rtx_SET (VOIDmode,
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gen_frame_mem (Pmode,
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plus_constant (Pmode,
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stack_pointer_rtx,
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4 * (i + 1))),
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reg2);
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RTX_FRAME_RELATED_P (tmp1) = 1;
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RTX_FRAME_RELATED_P (tmp2) = 1;
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XVECEXP (dwarf, 0, i + 1) = tmp1;
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XVECEXP (dwarf, 0, i + 2) = tmp2;
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i += 2;
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regno = regno2 + 1;
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}
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else
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regno++;
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return;
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return;
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}
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}
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@ -325,6 +325,21 @@
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(set_attr "neg_pool_range" "*,*,*,250")]
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(set_attr "neg_pool_range" "*,*,*,250")]
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)
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)
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(define_insn "*thumb2_storewb_pairsi"
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[(set (match_operand:SI 0 "register_operand" "=&kr")
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(plus:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "const_int_operand" "n")))
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(set (mem:SI (plus:SI (match_dup 0) (match_dup 2)))
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(match_operand:SI 3 "register_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 0)
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(match_operand:SI 5 "const_int_operand" "n")))
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(match_operand:SI 4 "register_operand" "r"))]
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"TARGET_THUMB2
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&& INTVAL (operands[5]) == INTVAL (operands[2]) + 4"
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"strd\\t%3, %4, [%0, %2]!"
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[(set_attr "type" "store2")]
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)
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(define_insn "*thumb2_cmpsi_neg_shiftsi"
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(define_insn "*thumb2_cmpsi_neg_shiftsi"
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[(set (reg:CC CC_REGNUM)
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[(set (reg:CC CC_REGNUM)
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(compare:CC (match_operand:SI 0 "s_register_operand" "r")
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(compare:CC (match_operand:SI 0 "s_register_operand" "r")
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