predicates.md (any_register_operand, [...]): Delete.
gcc/ * config/sh/predicates.md (any_register_operand, zero_extend_operand, logical_reg_operand): Delete. (arith_operand, arith_reg_dest, arith_or_int_operand, cmpsi_operand, arith_reg_or_0_operand, arith_reg_or_0_or_1_operand, logical_operand, logical_and_operand, movsrc_no_disp_mem_operand): Rewrite using match_operand and match_test. (sh_const_vec, sh_1el_vec): Remove redundant checks. Declare local variables on their first use. Return bool values. * config/sh/sh.h (LOAD_EXTEND_OP): Update comment. * config/sh/sh.md (andsi3, iorsi3): Use arith_reg_dest for result and arith_reg_operand for input operand. Remove empty constraints. (xorsi3): Delete. (*xorsi3_compact): Rename to xorsi3. (zero_extend<mode>si2): Use arith_reg_operand for input operand. (*zero_extend<mode>si2_disp_mem): Update comment. (mov_nop): Delete. From-SVN: r235687
This commit is contained in:
Oleg Endo
parent
c4ef2cba38
commit
5a2fc4d738
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@ -1,3 +1,22 @@
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2016-05-01 Oleg Endo <olegendo@gcc.gnu.org>
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* config/sh/predicates.md (any_register_operand, zero_extend_operand,
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logical_reg_operand): Delete.
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(arith_operand, arith_reg_dest, arith_or_int_operand, cmpsi_operand,
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arith_reg_or_0_operand, arith_reg_or_0_or_1_operand, logical_operand,
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logical_and_operand, movsrc_no_disp_mem_operand): Rewrite using
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match_operand and match_test.
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(sh_const_vec, sh_1el_vec): Remove redundant checks. Declare local
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variables on their first use. Return bool values.
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* config/sh/sh.h (LOAD_EXTEND_OP): Update comment.
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* config/sh/sh.md (andsi3, iorsi3): Use arith_reg_dest for result and
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arith_reg_operand for input operand. Remove empty constraints.
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(xorsi3): Delete.
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(*xorsi3_compact): Rename to xorsi3.
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(zero_extend<mode>si2): Use arith_reg_operand for input operand.
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(*zero_extend<mode>si2_disp_mem): Update comment.
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(mov_nop): Delete.
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2016-04-30 Oleg Endo <olegendo@gcc.gnu.org>
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* config/sh/t-sh: Remove SH5 support.
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@ -17,29 +17,6 @@
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; Like register_operand, but this predicate is defined with
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;; define_special_predicate, not define_predicate.
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(define_special_predicate "any_register_operand"
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(match_code "subreg,reg")
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{
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return register_operand (op, mode);
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})
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;; Returns 1 if OP is a valid source operand for an arithmetic insn.
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(define_predicate "arith_operand"
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(match_code "subreg,reg,const_int,truncate")
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{
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return arith_reg_operand (op, mode) || satisfies_constraint_I08 (op);
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})
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;; Like above, but for DImode destinations: forbid paradoxical DImode
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;; subregs, because this would lead to missing sign extensions when
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;; truncating from DImode to SImode.
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(define_predicate "arith_reg_dest"
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(match_code "subreg,reg")
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{
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return arith_reg_operand (op, mode);
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})
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;; Returns 1 if OP is a normal arithmetic register.
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(define_predicate "arith_reg_operand"
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@ -82,38 +59,36 @@
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return 0;
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})
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;; Like above, but for DImode destinations: forbid paradoxical DImode
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;; subregs, because this would lead to missing sign extensions when
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;; truncating from DImode to SImode.
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(define_predicate "arith_reg_dest"
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(and (match_code "subreg,reg")
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(match_operand 0 "arith_reg_operand")))
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;; Returns true if OP is a valid source operand for an arithmetic insn.
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(define_predicate "arith_operand"
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(and (match_code "subreg,reg,const_int,truncate")
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(ior (match_operand 0 "arith_reg_operand")
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(match_test "satisfies_constraint_I08 (op)"))))
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;; Likewise arith_operand but always permits const_int.
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(define_predicate "arith_or_int_operand"
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(match_code "subreg,reg,const_int,const_vector")
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{
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if (arith_operand (op, mode))
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return 1;
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(and (match_code "subreg,reg,const_int,const_vector")
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(ior (match_operand 0 "arith_operand")
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(match_operand 0 "const_int_operand"))))
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if (CONST_INT_P (op))
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return 1;
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return 0;
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})
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;; Returns 1 if OP is a valid source operand for a compare insn.
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(define_predicate "arith_reg_or_0_operand"
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(match_code "subreg,reg,const_int,const_vector")
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{
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if (arith_reg_operand (op, mode))
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return 1;
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if (satisfies_constraint_Z (op))
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return 1;
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return 0;
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})
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;; Returns true if OP is a valid source operand for a compare insn.
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(define_predicate "arith_reg_or_0_operand"
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(and (match_code "subreg,reg,const_int,const_vector")
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(ior (match_operand 0 "arith_reg_operand")
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(match_test "satisfies_constraint_Z (op)"))))
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;; Returns true if OP is either a register or constant 0 or constant 1.
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(define_predicate "arith_reg_or_0_or_1_operand"
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(match_code "subreg,reg,const_int,const_vector")
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{
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return arith_reg_or_0_operand (op, mode) || satisfies_constraint_M (op);
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})
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(and (match_code "subreg,reg,const_int,const_vector")
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(ior (match_operand 0 "arith_reg_or_0_operand")
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(match_test "satisfies_constraint_M (op)"))))
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;; Returns true if OP is a suitable constant for the minimum value of a
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;; clips.b or clips.w insn.
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@ -136,18 +111,6 @@
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(ior (match_test "INTVAL (op) == 255")
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(match_test "INTVAL (op) == 65535"))))
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;; Returns true if OP is an operand that can be used as the first operand in
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;; the cstoresi4 expander pattern.
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(define_predicate "cmpsi_operand"
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(match_code "subreg,reg,const_int")
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{
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if (REG_P (op) && REGNO (op) == T_REG
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&& GET_MODE (op) == SImode
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&& TARGET_SH1)
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return 1;
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return arith_operand (op, mode);
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})
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;; Returns true if OP is a floating point register that can be used in floating
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;; point arithmetic operations.
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(define_predicate "fp_arith_reg_operand"
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@ -274,10 +237,6 @@
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(ior (match_test "GET_MODE (op) == QImode")
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(match_test "GET_MODE (op) == HImode"))))
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;; Returns 1 if the operand can be used in a zero_extend.
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(define_predicate "zero_extend_operand"
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(match_operand 0 "arith_reg_operand"))
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;; Returns 1 if OP can be source of a simple move operation. Same as
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;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as
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;; are subregs of system registers.
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@ -376,12 +335,11 @@
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return general_operand (op, mode);
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})
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;; Returns 1 if OP is a MEM that does not use displacement addressing.
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;; Returns true if OP is a MEM that does not use displacement addressing.
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(define_predicate "movsrc_no_disp_mem_operand"
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(match_code "mem")
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{
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return general_movsrc_operand (op, mode) && satisfies_constraint_Snd (op);
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})
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(and (match_code "mem")
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(match_operand 0 "general_movsrc_operand")
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(match_test "satisfies_constraint_Snd (op)")))
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;; Returns 1 if OP can be a destination of a move. Same as
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;; general_operand, but no preinc allowed.
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@ -510,12 +468,11 @@
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&& sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true);
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})
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;; Returns 1 if OP is a valid source operand for a logical operation.
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;; Returns true if OP is a valid source operand for a logical operation.
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(define_predicate "logical_operand"
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(match_code "subreg,reg,const_int")
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{
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return arith_reg_operand (op, mode) || satisfies_constraint_K08 (op);
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})
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(and (match_code "subreg,reg,const_int")
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(ior (match_operand 0 "arith_reg_operand")
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(match_test "satisfies_constraint_K08 (op)"))))
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;; Returns true if OP is a valid constant source operand for a logical
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;; operations tst/and/or/xor #imm,r0.
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@ -526,36 +483,23 @@
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;; Like logical_operand but allows additional constant values which can be
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;; done with zero extensions. Used for the second operand of and insns.
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(define_predicate "logical_and_operand"
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(match_code "subreg,reg,const_int")
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{
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return logical_operand (op, mode) || satisfies_constraint_Jmb (op)
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|| satisfies_constraint_Jmw (op);
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})
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(and (match_code "subreg,reg,const_int")
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(ior (match_operand 0 "logical_operand")
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(match_test "satisfies_constraint_Jmb (op)")
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(match_test "satisfies_constraint_Jmw (op)"))))
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;; Returns true if OP is a logical operator.
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(define_predicate "logical_operator"
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(match_code "and,ior,xor"))
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(define_predicate "logical_reg_operand"
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(match_code "subreg,reg")
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{
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return arith_reg_operand (op, mode);
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})
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;; Returns true if OP is a constant vector.
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(define_predicate "sh_const_vec"
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(match_code "const_vector")
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{
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int i;
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if (GET_CODE (op) != CONST_VECTOR
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|| (GET_MODE (op) != mode && mode != VOIDmode))
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return 0;
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i = XVECLEN (op, 0) - 1;
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for (; i >= 0; i--)
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for (int i = XVECLEN (op, 0) - 1; i >= 0; i--)
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if (!CONST_INT_P (XVECEXP (op, 0, i)))
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return 0;
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return 1;
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return false;
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return true;
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})
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;; Determine if OP is a constant vector matching MODE with only one
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@ -564,32 +508,25 @@
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(define_predicate "sh_1el_vec"
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(match_code "const_vector")
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{
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int unit_size;
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int i, last, least, sign_ix;
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rtx sign;
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if (GET_CODE (op) != CONST_VECTOR
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|| (GET_MODE (op) != mode && mode != VOIDmode))
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return 0;
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/* Determine numbers of last and of least significant elements. */
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last = XVECLEN (op, 0) - 1;
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least = TARGET_LITTLE_ENDIAN ? 0 : last;
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int last = XVECLEN (op, 0) - 1;
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int least = TARGET_LITTLE_ENDIAN ? 0 : last;
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if (!CONST_INT_P (XVECEXP (op, 0, least)))
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return 0;
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sign_ix = least;
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return false;
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int sign_ix = least;
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if (GET_MODE_UNIT_SIZE (mode) == 1)
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sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
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if (!CONST_INT_P (XVECEXP (op, 0, sign_ix)))
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return 0;
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unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op));
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sign = (INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
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? constm1_rtx : const0_rtx);
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i = XVECLEN (op, 0) - 1;
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return false;
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int unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op));
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rtx sign = INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
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? constm1_rtx : const0_rtx;
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int i = XVECLEN (op, 0) - 1;
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do
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if (i != least && i != sign_ix && XVECEXP (op, 0, i) != sign)
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return 0;
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while (--i);
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return 1;
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return true;
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})
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;; Returns true if OP is a vector which is composed of one element that is
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@ -597,27 +534,21 @@
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(define_predicate "sh_rep_vec"
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(match_code "const_vector,parallel")
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{
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int i;
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rtx x, y;
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if ((GET_CODE (op) != CONST_VECTOR && GET_CODE (op) != PARALLEL)
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|| (GET_MODE (op) != mode && mode != VOIDmode))
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return 0;
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i = XVECLEN (op, 0) - 2;
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x = XVECEXP (op, 0, i + 1);
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int i = XVECLEN (op, 0) - 2;
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rtx x = XVECEXP (op, 0, i + 1);
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if (GET_MODE_UNIT_SIZE (mode) == 1)
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{
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y = XVECEXP (op, 0, i);
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rtx y = XVECEXP (op, 0, i);
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for (i -= 2; i >= 0; i -= 2)
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if (! rtx_equal_p (XVECEXP (op, 0, i + 1), x)
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|| ! rtx_equal_p (XVECEXP (op, 0, i), y))
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return 0;
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return false;
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}
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else
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for (; i >= 0; i--)
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if (XVECEXP (op, 0, i) != x)
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return 0;
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return 1;
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return false;
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return true;
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})
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;; Returns true if OP is a valid shift count operand for shift operations.
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@ -745,6 +676,13 @@
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}
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})
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;; Returns true if OP is an operand that can be used as the first operand in
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;; the cstoresi4 expander pattern.
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(define_predicate "cmpsi_operand"
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(and (match_code "subreg,reg,const_int")
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(ior (match_operand:SI 0 "t_reg_operand")
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(match_operand 0 "arith_operand"))))
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;; A predicate that returns true if OP is a valid construct around the T bit
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;; that can be used as an operand for conditional branches.
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(define_predicate "cbranch_treg_value"
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@ -1523,10 +1523,7 @@ struct sh_args {
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/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
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will either zero-extend or sign-extend. The value of this macro should
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be the code that says which one of the two operations is implicitly
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done, UNKNOWN if none.
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For SHmedia, we can truncate to QImode easier using zero extension.
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FP registers can load SImode values, but don't implicitly sign-extend
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them to DImode. */
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done, UNKNOWN if none. */
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#define LOAD_EXTEND_OP(MODE) ((MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
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/* Define if loading short immediate values into registers sign extends. */
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@ -2823,14 +2823,14 @@
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;; -------------------------------------------------------------------------
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(define_expand "andsi3"
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[(set (match_operand:SI 0 "arith_reg_operand" "")
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(and:SI (match_operand:SI 1 "logical_reg_operand" "")
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(match_operand:SI 2 "logical_and_operand" "")))]
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[(set (match_operand:SI 0 "arith_reg_dest")
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(and:SI (match_operand:SI 1 "arith_reg_operand")
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(match_operand:SI 2 "logical_and_operand")))]
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""
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{
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/* If it is possible to turn the and insn into a zero extension
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already, redundant zero extensions will be folded, which results
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in better code.
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in better code.
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Ideally the splitter of *andsi_compact would be enough, if redundant
|
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zero extensions were detected after the combine pass, which does not
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happen at the moment. */
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@ -2880,11 +2880,9 @@
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[(set_attr "type" "arith")])
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(define_expand "iorsi3"
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[(set (match_operand:SI 0 "arith_reg_operand" "")
|
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(ior:SI (match_operand:SI 1 "logical_reg_operand" "")
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(match_operand:SI 2 "logical_operand" "")))]
|
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""
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"")
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[(set (match_operand:SI 0 "arith_reg_dest")
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(ior:SI (match_operand:SI 1 "arith_reg_operand")
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(match_operand:SI 2 "logical_operand")))])
|
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|
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(define_insn "*iorsi3_compact"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
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|
|
@ -2903,14 +2901,7 @@
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"bset %V2,%0"
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[(set_attr "type" "arith")])
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(define_expand "xorsi3"
|
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[(set (match_operand:SI 0 "arith_reg_operand" "")
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(xor:SI (match_operand:SI 1 "logical_reg_operand" "")
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(match_operand:SI 2 "logical_operand" "")))]
|
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""
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"")
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(define_insn "*xorsi3_compact"
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(define_insn "xorsi3"
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[(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
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(xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
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(match_operand:SI 2 "logical_operand" "K08,r")))]
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|
|
@ -4784,7 +4775,7 @@
|
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|
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(define_expand "zero_extend<mode>si2"
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[(set (match_operand:SI 0 "arith_reg_dest")
|
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(zero_extend:SI (match_operand:QIHI 1 "zero_extend_operand")))])
|
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(zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand")))])
|
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|
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(define_insn_and_split "*zero_extend<mode>si2_compact"
|
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[(set (match_operand:SI 0 "arith_reg_dest" "=r")
|
||||
|
|
@ -4819,12 +4810,11 @@
|
|||
;; the displacement value to zero. However, doing so too early results in
|
||||
;; missed opportunities for other optimizations such as post-inc or index
|
||||
;; addressing loads.
|
||||
;; We don't allow the zero extending loads to match during RTL expansion
|
||||
;; (see zero_extend_operand predicate), as this would pessimize other
|
||||
;; optimization opportunities such as bit extractions of unsigned mems,
|
||||
;; where the zero extraction is irrelevant. If the zero extracting mem
|
||||
;; loads are emitted early it will be more difficult to change them back
|
||||
;; to sign extending loads (which are preferred).
|
||||
;; We don't allow the zero extending loads to match during RTL expansion,
|
||||
;; as this would pessimize other optimization opportunities such as bit
|
||||
;; extractions of unsigned mems, where the zero extraction is irrelevant.
|
||||
;; If the zero extracting mem loads are emitted early it will be more
|
||||
;; difficult to change them back to sign extending loads (which are preferred).
|
||||
;; The combine pass will also try to combine mem loads and zero extends,
|
||||
;; which is prevented by 'sh_legitimate_combined_insn'.
|
||||
(define_insn "*zero_extend<mode>si2_disp_mem"
|
||||
|
|
@ -6269,13 +6259,6 @@
|
|||
}
|
||||
})
|
||||
|
||||
(define_insn "mov_nop"
|
||||
[(set (match_operand 0 "any_register_operand" "") (match_dup 0))]
|
||||
"TARGET_SH2E"
|
||||
""
|
||||
[(set_attr "length" "0")
|
||||
(set_attr "type" "nil")])
|
||||
|
||||
(define_expand "reload_insf__frn"
|
||||
[(parallel [(set (match_operand:SF 0 "register_operand" "=a")
|
||||
(match_operand:SF 1 "immediate_operand" "FQ"))
|
||||
|
|
|
|||
Loading…
Reference in New Issue