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re PR target/81175 (EXC_BAD_ACCESS in ::slpeel_duplicate_current_defs_from_edges(edge, edge, edge, edge) at is-a.h:192)

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2017-06-26  Richard Biener  <rguenther@suse.de>

	PR target/81175
	* config/i386/i386.c (ix86_init_mmx_sse_builtins):
	Use def_builtin_pure for all gather builtins.

	* gfortran.dg/pr81175.f: New testcase.

From-SVN: r249645
This commit is contained in:
Richard Biener 2017-06-26 10:34:49 +00:00 committed by Richard Biener
parent 75f0112f1b
commit 5a5c2d16e7
4 changed files with 202 additions and 168 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2017-06-26 Richard Biener <rguenther@suse.de>
PR target/81175
* config/i386/i386.c (ix86_init_mmx_sse_builtins):
Use def_builtin_pure for all gather builtins.
2017-06-26 Richard Biener <rguenther@suse.de>
PR tree-optimization/81203

336
gcc/config/i386/i386.c
View File

@ -32564,134 +32564,134 @@ ix86_init_mmx_sse_builtins (void)
IX86_BUILTIN_RDRAND64_STEP);
/* AVX2 */
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv2df",
V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
IX86_BUILTIN_GATHERSIV2DF);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv2df",
V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
IX86_BUILTIN_GATHERSIV2DF);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4df",
V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
IX86_BUILTIN_GATHERSIV4DF);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4df",
V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
IX86_BUILTIN_GATHERSIV4DF);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv2df",
V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
IX86_BUILTIN_GATHERDIV2DF);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv2df",
V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
IX86_BUILTIN_GATHERDIV2DF);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4df",
V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
IX86_BUILTIN_GATHERDIV4DF);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4df",
V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
IX86_BUILTIN_GATHERDIV4DF);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4sf",
V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
IX86_BUILTIN_GATHERSIV4SF);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4sf",
V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
IX86_BUILTIN_GATHERSIV4SF);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv8sf",
V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
IX86_BUILTIN_GATHERSIV8SF);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv8sf",
V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
IX86_BUILTIN_GATHERSIV8SF);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4sf",
V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
IX86_BUILTIN_GATHERDIV4SF);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4sf",
V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
IX86_BUILTIN_GATHERDIV4SF);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4sf256",
V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
IX86_BUILTIN_GATHERDIV8SF);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4sf256",
V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
IX86_BUILTIN_GATHERDIV8SF);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv2di",
V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
IX86_BUILTIN_GATHERSIV2DI);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv2di",
V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
IX86_BUILTIN_GATHERSIV2DI);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4di",
V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
IX86_BUILTIN_GATHERSIV4DI);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4di",
V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
IX86_BUILTIN_GATHERSIV4DI);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv2di",
V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
IX86_BUILTIN_GATHERDIV2DI);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv2di",
V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
IX86_BUILTIN_GATHERDIV2DI);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4di",
V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
IX86_BUILTIN_GATHERDIV4DI);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4di",
V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
IX86_BUILTIN_GATHERDIV4DI);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4si",
V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
IX86_BUILTIN_GATHERSIV4SI);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv4si",
V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
IX86_BUILTIN_GATHERSIV4SI);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv8si",
V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
IX86_BUILTIN_GATHERSIV8SI);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gathersiv8si",
V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
IX86_BUILTIN_GATHERSIV8SI);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4si",
V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
IX86_BUILTIN_GATHERDIV4SI);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4si",
V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
IX86_BUILTIN_GATHERDIV4SI);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4si256",
V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
IX86_BUILTIN_GATHERDIV8SI);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatherdiv4si256",
V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
IX86_BUILTIN_GATHERDIV8SI);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltsiv4df ",
V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
IX86_BUILTIN_GATHERALTSIV4DF);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltsiv4df ",
V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
IX86_BUILTIN_GATHERALTSIV4DF);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltdiv4sf256 ",
V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
IX86_BUILTIN_GATHERALTDIV8SF);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltdiv4sf256 ",
V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
IX86_BUILTIN_GATHERALTDIV8SF);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltsiv4di ",
V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
IX86_BUILTIN_GATHERALTSIV4DI);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltsiv4di ",
V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
IX86_BUILTIN_GATHERALTSIV4DI);
def_builtin (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltdiv4si256 ",
V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
IX86_BUILTIN_GATHERALTDIV8SI);
def_builtin_pure (OPTION_MASK_ISA_AVX2, "__builtin_ia32_gatheraltdiv4si256 ",
V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
IX86_BUILTIN_GATHERALTDIV8SI);
/* AVX512F */
def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv16sf",
V16SF_FTYPE_V16SF_PCVOID_V16SI_HI_INT,
IX86_BUILTIN_GATHER3SIV16SF);
def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv16sf",
V16SF_FTYPE_V16SF_PCVOID_V16SI_HI_INT,
IX86_BUILTIN_GATHER3SIV16SF);
def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv8df",
V8DF_FTYPE_V8DF_PCVOID_V8SI_QI_INT,
IX86_BUILTIN_GATHER3SIV8DF);
def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv8df",
V8DF_FTYPE_V8DF_PCVOID_V8SI_QI_INT,
IX86_BUILTIN_GATHER3SIV8DF);
def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv16sf",
V8SF_FTYPE_V8SF_PCVOID_V8DI_QI_INT,
IX86_BUILTIN_GATHER3DIV16SF);
def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv16sf",
V8SF_FTYPE_V8SF_PCVOID_V8DI_QI_INT,
IX86_BUILTIN_GATHER3DIV16SF);
def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv8df",
V8DF_FTYPE_V8DF_PCVOID_V8DI_QI_INT,
IX86_BUILTIN_GATHER3DIV8DF);
def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv8df",
V8DF_FTYPE_V8DF_PCVOID_V8DI_QI_INT,
IX86_BUILTIN_GATHER3DIV8DF);
def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv16si",
V16SI_FTYPE_V16SI_PCVOID_V16SI_HI_INT,
IX86_BUILTIN_GATHER3SIV16SI);
def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv16si",
V16SI_FTYPE_V16SI_PCVOID_V16SI_HI_INT,
IX86_BUILTIN_GATHER3SIV16SI);
def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv8di",
V8DI_FTYPE_V8DI_PCVOID_V8SI_QI_INT,
IX86_BUILTIN_GATHER3SIV8DI);
def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gathersiv8di",
V8DI_FTYPE_V8DI_PCVOID_V8SI_QI_INT,
IX86_BUILTIN_GATHER3SIV8DI);
def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv16si",
V8SI_FTYPE_V8SI_PCVOID_V8DI_QI_INT,
IX86_BUILTIN_GATHER3DIV16SI);
def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv16si",
V8SI_FTYPE_V8SI_PCVOID_V8DI_QI_INT,
IX86_BUILTIN_GATHER3DIV16SI);
def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv8di",
V8DI_FTYPE_V8DI_PCVOID_V8DI_QI_INT,
IX86_BUILTIN_GATHER3DIV8DI);
def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatherdiv8di",
V8DI_FTYPE_V8DI_PCVOID_V8DI_QI_INT,
IX86_BUILTIN_GATHER3DIV8DI);
def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltsiv8df ",
V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
IX86_BUILTIN_GATHER3ALTSIV8DF);
def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltsiv8df ",
V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
IX86_BUILTIN_GATHER3ALTSIV8DF);
def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltdiv8sf ",
V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
IX86_BUILTIN_GATHER3ALTDIV16SF);
def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltdiv8sf ",
V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
IX86_BUILTIN_GATHER3ALTDIV16SF);
def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltsiv8di ",
V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
IX86_BUILTIN_GATHER3ALTSIV8DI);
def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltsiv8di ",
V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
IX86_BUILTIN_GATHER3ALTSIV8DI);
def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltdiv8si ",
V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
IX86_BUILTIN_GATHER3ALTDIV16SI);
def_builtin_pure (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_gatheraltdiv8si ",
V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
IX86_BUILTIN_GATHER3ALTDIV16SI);
def_builtin (OPTION_MASK_ISA_AVX512F, "__builtin_ia32_scattersiv16sf",
VOID_FTYPE_PVOID_HI_V16SI_V16SF_INT,
@ -32726,85 +32726,85 @@ ix86_init_mmx_sse_builtins (void)
IX86_BUILTIN_SCATTERDIV8DI);
/* AVX512VL */
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv2df",
V2DF_FTYPE_V2DF_PCVOID_V4SI_QI_INT,
IX86_BUILTIN_GATHER3SIV2DF);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv2df",
V2DF_FTYPE_V2DF_PCVOID_V4SI_QI_INT,
IX86_BUILTIN_GATHER3SIV2DF);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4df",
V4DF_FTYPE_V4DF_PCVOID_V4SI_QI_INT,
IX86_BUILTIN_GATHER3SIV4DF);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4df",
V4DF_FTYPE_V4DF_PCVOID_V4SI_QI_INT,
IX86_BUILTIN_GATHER3SIV4DF);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div2df",
V2DF_FTYPE_V2DF_PCVOID_V2DI_QI_INT,
IX86_BUILTIN_GATHER3DIV2DF);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div2df",
V2DF_FTYPE_V2DF_PCVOID_V2DI_QI_INT,
IX86_BUILTIN_GATHER3DIV2DF);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4df",
V4DF_FTYPE_V4DF_PCVOID_V4DI_QI_INT,
IX86_BUILTIN_GATHER3DIV4DF);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4df",
V4DF_FTYPE_V4DF_PCVOID_V4DI_QI_INT,
IX86_BUILTIN_GATHER3DIV4DF);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4sf",
V4SF_FTYPE_V4SF_PCVOID_V4SI_QI_INT,
IX86_BUILTIN_GATHER3SIV4SF);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4sf",
V4SF_FTYPE_V4SF_PCVOID_V4SI_QI_INT,
IX86_BUILTIN_GATHER3SIV4SF);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv8sf",
V8SF_FTYPE_V8SF_PCVOID_V8SI_QI_INT,
IX86_BUILTIN_GATHER3SIV8SF);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv8sf",
V8SF_FTYPE_V8SF_PCVOID_V8SI_QI_INT,
IX86_BUILTIN_GATHER3SIV8SF);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4sf",
V4SF_FTYPE_V4SF_PCVOID_V2DI_QI_INT,
IX86_BUILTIN_GATHER3DIV4SF);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4sf",
V4SF_FTYPE_V4SF_PCVOID_V2DI_QI_INT,
IX86_BUILTIN_GATHER3DIV4SF);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div8sf",
V4SF_FTYPE_V4SF_PCVOID_V4DI_QI_INT,
IX86_BUILTIN_GATHER3DIV8SF);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div8sf",
V4SF_FTYPE_V4SF_PCVOID_V4DI_QI_INT,
IX86_BUILTIN_GATHER3DIV8SF);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv2di",
V2DI_FTYPE_V2DI_PCVOID_V4SI_QI_INT,
IX86_BUILTIN_GATHER3SIV2DI);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv2di",
V2DI_FTYPE_V2DI_PCVOID_V4SI_QI_INT,
IX86_BUILTIN_GATHER3SIV2DI);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4di",
V4DI_FTYPE_V4DI_PCVOID_V4SI_QI_INT,
IX86_BUILTIN_GATHER3SIV4DI);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4di",
V4DI_FTYPE_V4DI_PCVOID_V4SI_QI_INT,
IX86_BUILTIN_GATHER3SIV4DI);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div2di",
V2DI_FTYPE_V2DI_PCVOID_V2DI_QI_INT,
IX86_BUILTIN_GATHER3DIV2DI);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div2di",
V2DI_FTYPE_V2DI_PCVOID_V2DI_QI_INT,
IX86_BUILTIN_GATHER3DIV2DI);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4di",
V4DI_FTYPE_V4DI_PCVOID_V4DI_QI_INT,
IX86_BUILTIN_GATHER3DIV4DI);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4di",
V4DI_FTYPE_V4DI_PCVOID_V4DI_QI_INT,
IX86_BUILTIN_GATHER3DIV4DI);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4si",
V4SI_FTYPE_V4SI_PCVOID_V4SI_QI_INT,
IX86_BUILTIN_GATHER3SIV4SI);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv4si",
V4SI_FTYPE_V4SI_PCVOID_V4SI_QI_INT,
IX86_BUILTIN_GATHER3SIV4SI);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv8si",
V8SI_FTYPE_V8SI_PCVOID_V8SI_QI_INT,
IX86_BUILTIN_GATHER3SIV8SI);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3siv8si",
V8SI_FTYPE_V8SI_PCVOID_V8SI_QI_INT,
IX86_BUILTIN_GATHER3SIV8SI);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4si",
V4SI_FTYPE_V4SI_PCVOID_V2DI_QI_INT,
IX86_BUILTIN_GATHER3DIV4SI);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div4si",
V4SI_FTYPE_V4SI_PCVOID_V2DI_QI_INT,
IX86_BUILTIN_GATHER3DIV4SI);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div8si",
V4SI_FTYPE_V4SI_PCVOID_V4DI_QI_INT,
IX86_BUILTIN_GATHER3DIV8SI);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3div8si",
V4SI_FTYPE_V4SI_PCVOID_V4DI_QI_INT,
IX86_BUILTIN_GATHER3DIV8SI);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altsiv4df ",
V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
IX86_BUILTIN_GATHER3ALTSIV4DF);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altsiv4df ",
V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
IX86_BUILTIN_GATHER3ALTSIV4DF);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altdiv8sf ",
V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
IX86_BUILTIN_GATHER3ALTDIV8SF);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altdiv8sf ",
V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
IX86_BUILTIN_GATHER3ALTDIV8SF);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altsiv4di ",
V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
IX86_BUILTIN_GATHER3ALTSIV4DI);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altsiv4di ",
V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
IX86_BUILTIN_GATHER3ALTSIV4DI);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altdiv8si ",
V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
IX86_BUILTIN_GATHER3ALTDIV8SI);
def_builtin_pure (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_gather3altdiv8si ",
V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
IX86_BUILTIN_GATHER3ALTDIV8SI);
def_builtin (OPTION_MASK_ISA_AVX512VL, "__builtin_ia32_scattersiv8sf",
VOID_FTYPE_PVOID_QI_V8SI_V8SF_INT,
@ -32886,18 +32886,18 @@ ix86_init_mmx_sse_builtins (void)
IX86_BUILTIN_SCATTERALTDIV16SI);
/* AVX512PF */
def_builtin (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_gatherpfdpd",
VOID_FTYPE_QI_V8SI_PCVOID_INT_INT,
IX86_BUILTIN_GATHERPFDPD);
def_builtin (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_gatherpfdps",
VOID_FTYPE_HI_V16SI_PCVOID_INT_INT,
IX86_BUILTIN_GATHERPFDPS);
def_builtin (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_gatherpfqpd",
VOID_FTYPE_QI_V8DI_PCVOID_INT_INT,
IX86_BUILTIN_GATHERPFQPD);
def_builtin (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_gatherpfqps",
VOID_FTYPE_QI_V8DI_PCVOID_INT_INT,
IX86_BUILTIN_GATHERPFQPS);
def_builtin_pure (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_gatherpfdpd",
VOID_FTYPE_QI_V8SI_PCVOID_INT_INT,
IX86_BUILTIN_GATHERPFDPD);
def_builtin_pure (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_gatherpfdps",
VOID_FTYPE_HI_V16SI_PCVOID_INT_INT,
IX86_BUILTIN_GATHERPFDPS);
def_builtin_pure (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_gatherpfqpd",
VOID_FTYPE_QI_V8DI_PCVOID_INT_INT,
IX86_BUILTIN_GATHERPFQPD);
def_builtin_pure (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_gatherpfqps",
VOID_FTYPE_QI_V8DI_PCVOID_INT_INT,
IX86_BUILTIN_GATHERPFQPS);
def_builtin (OPTION_MASK_ISA_AVX512PF, "__builtin_ia32_scatterpfdpd",
VOID_FTYPE_QI_V8SI_PCVOID_INT_INT,
IX86_BUILTIN_SCATTERPFDPD);

5
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,8 @@
2017-06-26 Richard Biener <rguenther@suse.de>
PR target/81175
* gfortran.dg/pr81175.f: New testcase.
2017-06-26 Richard Biener <rguenther@suse.de>
PR tree-optimization/81203

23
gcc/testsuite/gfortran.dg/pr81175.f Normal file
View File

@ -0,0 +1,23 @@
! { dg-do compile }
! { dg-options "-Ofast -fwrapv" }
! { dg-additional-options "-march=broadwell" { target x86_64-*-* i?86-*-* } }
SUBROUTINE ECPDRA(IC4C,FP,FQ,G)
IMPLICIT DOUBLE PRECISION (A-H,O-Z)
DIMENSION FP(*),FQ(*),G(*)
DIMENSION CKLU(23,12,12)
!
DO 240 I=IAMIN,IAMAX
DO 240 J=JAMIN,MMAX
DO 230 K=1,NPNP
DO 230 L=1,K
DO 230 MU=1,2*L-1
CKLTEM= CKLU(MU,L,K)
IF(IC4C.LE.0) THEN
IF(ABS(CKLTEM).GT.TOL) SUM= SUM+FP(N)*CKLTEM
ELSE
IF(ABS(CKLTEM).GT.TOL) SUM= SUM+FQ(N)*CKLTEM
END IF
230 N= N+1
G(NN)= G(NN)+DUMJ*SUM
240 NN= NN+1
END