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re PR target/42895 (Low registers are preferred than register ip in thumb2 mode)

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PR target/42895
	* doc/tm.texi (ADJUST_REG_ALLOC_ORDER): Renamed from
	ORDER_REGS_FOR_LOCAL_ALLOC.  All instances of this macro changed.
	(HONOR_REG_ALLOC_ORDER): Describe new macro.
	* ira.c (setup_alloc_regs): Use ADJUST_REG_ALLOC_ORDER if defined.
	* ira-color.c (assign_hard_reg): Take prologue/epilogue costs into
	account only if HONOR_REG_ALLOC_ORDER is not defined.
	* config/arm/arm.h (HONOR_REG_ALLOC_ORDER): Define.
	* system.h (ORDER_REGS_FOR_LOCAL_ALLOC): Poison.

From-SVN: r158911
This commit is contained in:
Bernd Schmidt 2010-04-29 21:37:01 +00:00 committed by Bernd Schmidt
parent eece1eb9ac
commit 5a7338267d
12 changed files with 44 additions and 16 deletions
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12
gcc/ChangeLog
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@ -1,3 +1,15 @@
2010-04-29 Bernd Schmidt <bernds@codesourcery.com>
PR target/42895
* doc/tm.texi (ADJUST_REG_ALLOC_ORDER): Renamed from
ORDER_REGS_FOR_LOCAL_ALLOC. All instances of this macro changed.
(HONOR_REG_ALLOC_ORDER): Describe new macro.
* ira.c (setup_alloc_regs): Use ADJUST_REG_ALLOC_ORDER if defined.
* ira-color.c (assign_hard_reg): Take prologue/epilogue costs into
account only if HONOR_REG_ALLOC_ORDER is not defined.
* config/arm/arm.h (HONOR_REG_ALLOC_ORDER): Define.
* system.h (ORDER_REGS_FOR_LOCAL_ALLOC): Poison.
2010-04-29 Jon Grant <04@jguk.org> 2010-04-29 Jon Grant <04@jguk.org>
* collect2.c (vflag): Change type from int to bool. * collect2.c (vflag): Change type from int to bool.

6
gcc/config/arm/arm.h
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@ -1121,7 +1121,11 @@ extern int arm_structure_size_boundary;
} }
/* Use different register alloc ordering for Thumb. */ /* Use different register alloc ordering for Thumb. */
#define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc () #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc ()
/* Tell IRA to use the order we define rather than messing it up with its
own cost calculations. */
#define HONOR_REG_ALLOC_ORDER
/* Interrupt functions can only use registers that have already been /* Interrupt functions can only use registers that have already been
saved by the prologue, even if they would normally be saved by the prologue, even if they would normally be

2
gcc/config/avr/avr.h
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@ -232,7 +232,7 @@ extern GTY(()) section *progmem_section;
32,33,34,35 \ 32,33,34,35 \
} }
#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
#define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) #define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

6
gcc/config/i386/i386.h
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@ -955,7 +955,7 @@ enum target_cpu_default
registers listed in CALL_USED_REGISTERS, keeping the others registers listed in CALL_USED_REGISTERS, keeping the others
available for storage of persistent values. available for storage of persistent values.
The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, The ADJUST_REG_ALLOC_ORDER actually overwrite the order,
so this is just empty initializer for array. */ so this is just empty initializer for array. */
#define REG_ALLOC_ORDER \ #define REG_ALLOC_ORDER \
@ -964,11 +964,11 @@ enum target_cpu_default
33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
48, 49, 50, 51, 52 } 48, 49, 50, 51, 52 }
/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
to be rearranged based on a particular function. When using sse math, to be rearranged based on a particular function. When using sse math,
we want to allocate SSE before x87 registers and vice versa. */ we want to allocate SSE before x87 registers and vice versa. */
#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc ()
#define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)

4
gcc/config/mips/mips.h
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@ -2059,12 +2059,12 @@ enum reg_class
182,183,184,185,186,187 \ 182,183,184,185,186,187 \
} }
/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
to be rearranged based on a particular function. On the mips16, we to be rearranged based on a particular function. On the mips16, we
want to allocate $24 (T_REG) before other registers for want to allocate $24 (T_REG) before other registers for
instructions for which it is possible. */ instructions for which it is possible. */
#define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc () #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
/* True if VALUE is an unsigned 6-bit number. */ /* True if VALUE is an unsigned 6-bit number. */

2
gcc/config/picochip/picochip.h
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@ -261,7 +261,7 @@ extern enum picochip_dfa_type picochip_schedule_type;
/* We can dynamically change the REG_ALLOC_ORDER using the following hook. /* We can dynamically change the REG_ALLOC_ORDER using the following hook.
It would be desirable to change it for leaf functions so we can put It would be desirable to change it for leaf functions so we can put
r12 at the end of this list.*/ r12 at the end of this list.*/
#define ORDER_REGS_FOR_LOCAL_ALLOC picochip_order_regs_for_local_alloc () #define ADJUST_REG_ALLOC_ORDER picochip_order_regs_for_local_alloc ()
/* How Values Fit in Registers */ /* How Values Fit in Registers */

2
gcc/config/sparc/sparc.h
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@ -1181,7 +1181,7 @@ extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
96, 97, 98, 99, /* %fcc0-3 */ \ 96, 97, 98, 99, /* %fcc0-3 */ \
100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */ 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
extern char sparc_leaf_regs[]; extern char sparc_leaf_regs[];
#define LEAF_REGISTERS sparc_leaf_regs #define LEAF_REGISTERS sparc_leaf_regs

4
gcc/config/xtensa/xtensa.h
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@ -286,7 +286,7 @@ extern unsigned xtensa_current_frame_size;
incoming argument in a2 is live throughout the function and incoming argument in a2 is live throughout the function and
local-alloc decides to use a2, then the incoming argument must local-alloc decides to use a2, then the incoming argument must
either be spilled or copied to another register. To get around either be spilled or copied to another register. To get around
this, we define ORDER_REGS_FOR_LOCAL_ALLOC to redefine this, we define ADJUST_REG_ALLOC_ORDER to redefine
reg_alloc_order for leaf functions such that lowest numbered reg_alloc_order for leaf functions such that lowest numbered
registers are used first with the exception that the incoming registers are used first with the exception that the incoming
argument registers are not used until after other register choices argument registers are not used until after other register choices
@ -300,7 +300,7 @@ extern unsigned xtensa_current_frame_size;
35, \ 35, \
} }
#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
/* For Xtensa, the only point of this is to prevent GCC from otherwise /* For Xtensa, the only point of this is to prevent GCC from otherwise
giving preference to call-used registers. To minimize window giving preference to call-used registers. To minimize window

11
gcc/doc/tm.texi
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@ -2092,7 +2092,7 @@ machines, define @code{REG_ALLOC_ORDER} to be an initializer that lists
the highest numbered allocable register first. the highest numbered allocable register first.
@end defmac @end defmac
@defmac ORDER_REGS_FOR_LOCAL_ALLOC @defmac ADJUST_REG_ALLOC_ORDER
A C statement (sans semicolon) to choose the order in which to allocate A C statement (sans semicolon) to choose the order in which to allocate
hard registers for pseudo-registers local to a basic block. hard registers for pseudo-registers local to a basic block.
@ -2106,6 +2106,15 @@ The macro body should not assume anything about the contents of
On most machines, it is not necessary to define this macro. On most machines, it is not necessary to define this macro.
@end defmac @end defmac
@defmac HONOR_REG_ALLOC_ORDER
Normally, IRA tries to estimate the costs for saving a register in the
prologue and restoring it in the epilogue. This discourages it from
using call-saved registers. If a machine wants to ensure that IRA
allocates registers in the order given by REG_ALLOC_ORDER even if some
call-saved registers appear earlier than call-used ones, this macro
should be defined.
@end defmac
@defmac IRA_HARD_REGNO_ADD_COST_MULTIPLIER (@var{regno}) @defmac IRA_HARD_REGNO_ADD_COST_MULTIPLIER (@var{regno})
In some case register allocation order is not enough for the In some case register allocation order is not enough for the
Integrated Register Allocator (@acronym{IRA}) to generate a good code. Integrated Register Allocator (@acronym{IRA}) to generate a good code.

2
gcc/ira-color.c
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@ -586,6 +586,7 @@ assign_hard_reg (ira_allocno_t allocno, bool retry_p)
continue; continue;
cost = costs[i]; cost = costs[i];
full_cost = full_costs[i]; full_cost = full_costs[i];
#ifndef HONOR_REG_ALLOC_ORDER
if (! allocated_hardreg_p[hard_regno] if (! allocated_hardreg_p[hard_regno]
&& ira_hard_reg_not_in_set_p (hard_regno, mode, call_used_reg_set)) && ira_hard_reg_not_in_set_p (hard_regno, mode, call_used_reg_set))
/* We need to save/restore the hard register in /* We need to save/restore the hard register in
@ -598,6 +599,7 @@ assign_hard_reg (ira_allocno_t allocno, bool retry_p)
cost += add_cost; cost += add_cost;
full_cost += add_cost; full_cost += add_cost;
} }
#endif
if (min_cost > cost) if (min_cost > cost)
min_cost = cost; min_cost = cost;
if (min_full_cost > full_cost) if (min_full_cost > full_cost)

6
gcc/ira.c
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@ -431,9 +431,6 @@ setup_class_hard_regs (void)
HARD_REG_SET processed_hard_reg_set; HARD_REG_SET processed_hard_reg_set;
ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER);
/* We could call ORDER_REGS_FOR_LOCAL_ALLOC here (it is usually
putting hard callee-used hard registers first). But our
heuristics work better. */
for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
{ {
COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]);
@ -490,6 +487,9 @@ setup_available_class_regs (void)
static void static void
setup_alloc_regs (bool use_hard_frame_p) setup_alloc_regs (bool use_hard_frame_p)
{ {
#ifdef ADJUST_REG_ALLOC_ORDER
ADJUST_REG_ALLOC_ORDER;
#endif
COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set); COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set);
if (! use_hard_frame_p) if (! use_hard_frame_p)
SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM); SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM);

3
gcc/system.h
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@ -761,7 +761,8 @@ extern void fancy_abort (const char *, int, const char *) ATTRIBUTE_NORETURN;
TARGET_ASM_EXCEPTION_SECTION TARGET_ASM_EH_FRAME_SECTION \ TARGET_ASM_EXCEPTION_SECTION TARGET_ASM_EH_FRAME_SECTION \
SMALL_ARG_MAX ASM_OUTPUT_SHARED_BSS ASM_OUTPUT_SHARED_COMMON \ SMALL_ARG_MAX ASM_OUTPUT_SHARED_BSS ASM_OUTPUT_SHARED_COMMON \
ASM_OUTPUT_SHARED_LOCAL ASM_MAKE_LABEL_LINKONCE \ ASM_OUTPUT_SHARED_LOCAL ASM_MAKE_LABEL_LINKONCE \
STACK_CHECK_PROBE_INTERVAL STACK_CHECK_PROBE_LOAD STACK_CHECK_PROBE_INTERVAL STACK_CHECK_PROBE_LOAD \
ORDER_REGS_FOR_LOCAL_ALLOC
/* Hooks that are no longer used. */ /* Hooks that are no longer used. */
#pragma GCC poison LANG_HOOKS_FUNCTION_MARK LANG_HOOKS_FUNCTION_FREE \ #pragma GCC poison LANG_HOOKS_FUNCTION_MARK LANG_HOOKS_FUNCTION_FREE \