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arm.md (negsf2, negdf2): Permit these expands when compiling for VFP. 

* arm.md (negsf2, negdf2): Permit these expands when compiling for VFP.
	* gcc.dg/arm-vfp1.c: Revert last change.

From-SVN: r99569
This commit is contained in:
Richard Earnshaw 2005-05-11 10:13:23 +00:00 committed by Richard Earnshaw
parent c554294001
commit 5a942c07c2
4 changed files with 11 additions and 10 deletions
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4
gcc/ChangeLog
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@ -1,3 +1,7 @@
2005-05-11 Richard Earnshaw <richard.earnshaw@arm.com>
* arm.md (negsf2, negdf2): Permit these expands when compiling for VFP.
2005-05-11 Richard Guenther <rguenth@gcc.gnu.org>
PR middle-end/19807

4
gcc/config/arm/arm.md
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@ -2969,14 +2969,14 @@
(define_expand "negsf2"
[(set (match_operand:SF 0 "s_register_operand" "")
(neg:SF (match_operand:SF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
""
)
(define_expand "negdf2"
[(set (match_operand:DF 0 "s_register_operand" "")
(neg:DF (match_operand:DF 1 "s_register_operand" "")))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA"
"TARGET_ARM && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
"")
;; abssi2 doesn't really clobber the condition codes if a different register

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2005-05-11 Richard Earnshaw <richard.earnshaw@arm.com>
* gcc.dg/arm-vfp1.c: Revert last change.
2005-05-11 Richard Guenther <rguenth@gcc.gnu.org>
PR middle-end/19807

9
gcc/testsuite/gcc.dg/arm-vfp1.c
View File

@ -14,14 +14,7 @@ void test_sf() {
/* { dg-final { scan-assembler "fabss" } } */
f1 = fabsf (f1);
/* negsf2_vfp */
/* There is no test for "fnegs" because the compiler will use an
integer operation instead to implement this operation. Adding
complexity to the operand (e.g., "-(f1 + f2)") doesn't change the
situation, as the compiler still wants the result in an integer
register before writing it back to memory. If we used an ABI that
required passing floating-point values in VFP registers that
would likely persuade the compiler to keep the value in the VFP
registers. */
/* { dg-final { scan-assembler "fnegs" } } */
f1 = -f1;
/* addsf3_vfp */
/* { dg-final { scan-assembler "fadds" } } */