genrecog.c: Include regs.h in generated file.
2007-05-30 Eric Christopher <echristo@gmail.com> * genrecog.c: Include regs.h in generated file. * genemit.c: Ditto. Fix up formatting. * config/mn10300/constraints.md: New. * config/mn10300/mn10300.md: Include. * config/mn10300/mn10300.c(mn10300_secondary_reload_class): Fix up for removed macro. * config/mn10300/predicates.md (call_address_operand): Ditto. * config/mn10300/mn10300.h (REG_CLASS_FROM_LETTER): Delete. (CONST_OK_FOR_I): Ditto. (CONST_OK_FOR_J): Ditto. (CONST_OK_FOR_K): Ditto. (CONST_OK_FOR_L): Ditto. (CONST_OK_FOR_M): Ditto. (CONST_OK_FOR_N): Ditto. (CONST_DOUBLE_OK_FOR_LETTER_P): Ditto. (OK_FOR_Q): Ditto. (OK_FOR_R): Ditto. (OK_FOR_T): Ditto. (EXTRA_CONSTRAINT): Ditto. From-SVN: r125192
This commit is contained in:
Eric Christopher
parent
9dd3cc811b
commit
5abc5de971
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@ -1,3 +1,25 @@
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2007-05-30 Eric Christopher <echristo@gmail.com>
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* genrecog.c: Include regs.h in generated file.
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* genemit.c: Ditto. Fix up formatting.
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* config/mn10300/constraints.md: New.
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* config/mn10300/mn10300.md: Include.
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* config/mn10300/mn10300.c(mn10300_secondary_reload_class):
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Fix up for removed macro.
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* config/mn10300/predicates.md (call_address_operand): Ditto.
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* config/mn10300/mn10300.h (REG_CLASS_FROM_LETTER): Delete.
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(CONST_OK_FOR_I): Ditto.
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(CONST_OK_FOR_J): Ditto.
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(CONST_OK_FOR_K): Ditto.
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(CONST_OK_FOR_L): Ditto.
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(CONST_OK_FOR_M): Ditto.
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(CONST_OK_FOR_N): Ditto.
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(CONST_DOUBLE_OK_FOR_LETTER_P): Ditto.
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(OK_FOR_Q): Ditto.
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(OK_FOR_R): Ditto.
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(OK_FOR_T): Ditto.
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(EXTRA_CONSTRAINT): Ditto.
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2007-05-30 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.h (MASK_64BIT, MASK_MMX, MASK_3DNOW*, MASK_SSE*):
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@ -97,7 +119,7 @@
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NOTE_INSN_PROLOGUE_END at beginning of the thunk.
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2007-05-29 Hui-May Chang <hm.chang@apple.com>
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* config/i386/i386.c (ix86_function_regparm): Added checking of
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* config/i386/i386.c (ix86_function_regparm): Added checking of
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ix86_force_align_arg_pointer to determine the number of
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register parameters.
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@ -199,9 +221,9 @@
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* target/i386/i386.c (ix86_expand_vector_move): Expand unaligned
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memory access via x86_expand_vector_move_misalign() only for
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TImode values on 32-bit targets.
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2007-05-28 Razya Ladelsky <razya@il.ibm.com>
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2007-05-28 Razya Ladelsky <razya@il.ibm.com>
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* matrix-reorg.c: New file. Implement matrix flattening and
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transposing optimization.
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* tree-pass.h: Add matrix reorg pass.
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@ -0,0 +1,112 @@
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;; Constraint definitions for the MN10300.
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;; Copyright (C) 2007 Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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;;
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;; GCC is free software; you can redistribute it and/or modify
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;; it under the terms of the GNU General Public License as published by
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;; the Free Software Foundation; either version 2, or (at your option)
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;; any later version.
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;;
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;; GCC is distributed in the hope that it will be useful,
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;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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;; GNU General Public License for more details.
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;;
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;; You should have received a copy of the GNU General Public License
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;; along with GCC; see the file COPYING. If not, write to
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;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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;; Boston, MA 02110-1301, USA.
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(define_register_constraint "d" "DATA_REGS"
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"A data register.")
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(define_register_constraint "a" "ADDRESS_REGS"
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"An address register.")
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(define_register_constraint "y" "SP_REGS"
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"An SP register (if available).")
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(define_register_constraint "x" "TARGET_AM33 ? EXTENDED_REGS : NO_REGS"
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"An extended register.")
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(define_register_constraint "f" "TARGET_AM33_2 ? FP_REGS : NO_REGS"
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"A floating point register.")
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(define_register_constraint "A" "TARGET_AM33_2 ? FP_ACC_REGS : NO_REGS"
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"A floating point accumulator register.")
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(define_memory_constraint "Q"
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"@internal"
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(and (match_code "mem")
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(match_test "!CONSTANT_ADDRESS_P (XEXP (op, 0))")))
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(define_memory_constraint "R"
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"@internal"
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(and (match_code "mem")
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(match_test "mode == QImode")
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(ior (match_test "CONSTANT_ADDRESS_P (XEXP (op, 0))")
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(and (match_test "GET_CODE (XEXP (op, 0)) == REG")
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(match_test "REG_OK_FOR_BIT_BASE_P (XEXP (op, 0))")
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(match_test "XEXP (op, 0) != stack_pointer_rtx"))
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(and (match_test "GET_CODE (XEXP (op, 0)) == PLUS")
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(match_test "GET_CODE (XEXP (XEXP (op, 0), 0)) == REG")
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(match_test "REG_OK_FOR_BIT_BASE_P (XEXP (XEXP (op, 0), 0))")
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(match_test "XEXP (XEXP (op, 0), 0) != stack_pointer_rtx")
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(match_test "GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT")
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(match_test "INT_8_BITS (INTVAL (XEXP (XEXP (op, 0), 1)))")))))
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(define_memory_constraint "T"
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"@internal"
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(and (match_code "mem")
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(match_test "mode == QImode")
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(and (match_test "GET_CODE (XEXP (op, 0)) == REG")
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(match_test "REG_OK_FOR_BIT_BASE_P (XEXP (op, 0))")
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(match_test "XEXP (op, 0) != stack_pointer_rtx"))))
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(define_constraint "S"
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"@internal"
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(if_then_else (match_test "flag_pic")
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(and (match_test "GET_CODE (op) == UNSPEC")
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(ior (match_test "XINT (op, 1) == UNSPEC_PLT")
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(match_test "XINT (op, 1) == UNSPEC_PIC")))
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(match_test "GET_CODE (op) == SYMBOL_REF")))
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;; Integer constraints
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(define_constraint "I"
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"An integer zero."
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(and (match_code "const_int")
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(match_test "ival == 0")))
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(define_constraint "J"
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"An integer one."
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(and (match_code "const_int")
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(match_test "ival == 1")))
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(define_constraint "K"
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"An integer two."
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(and (match_code "const_int")
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(match_test "ival == 2")))
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(define_constraint "L"
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"An integer four."
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(and (match_code "const_int")
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(match_test "ival == 4")))
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(define_constraint "M"
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"An integer three."
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(and (match_code "const_int")
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(match_test "ival == 3")))
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(define_constraint "N"
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"An integer of either 255 or 65535."
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(and (match_code "const_int")
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(ior (match_test "ival == 255")
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(match_test "ival == 65535"))))
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;; Floating-point constraints
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(define_constraint "G"
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"Floating-point zero."
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(and (match_code "const_double")
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(match_test "op == CONST0_RTX (mode)")))
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@ -274,7 +274,7 @@ print_operand (FILE *file, rtx x, int code)
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else
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print_operand (file, x, 0);
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break;
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case 'D':
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switch (GET_CODE (x))
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{
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@ -387,7 +387,7 @@ print_operand (FILE *file, rtx x, int code)
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gcc_unreachable ();
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case VOIDmode:
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case DImode:
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print_operand_address (file,
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print_operand_address (file,
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GEN_INT (CONST_DOUBLE_HIGH (x)));
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break;
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default:
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@ -882,7 +882,7 @@ expand_prologue (void)
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default:
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gcc_unreachable ();
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}
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/* Now prepare register a0, if we have decided to use it. */
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switch (strategy)
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{
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@ -900,11 +900,11 @@ expand_prologue (void)
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emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)));
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reg = gen_rtx_POST_INC (SImode, reg);
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break;
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default:
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gcc_unreachable ();
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}
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/* Now actually save the FP registers. */
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for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
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if (regs_ever_live[i] && ! call_used_regs[i])
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@ -924,7 +924,7 @@ expand_prologue (void)
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}
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else
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addr = stack_pointer_rtx;
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xsize += 4;
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}
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@ -1109,7 +1109,7 @@ expand_epilogue (void)
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+ REG_SAVE_BYTES - 252)));
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size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save;
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break;
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case restore_a1:
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reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
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emit_insn (gen_movsi (reg, stack_pointer_rtx));
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@ -1130,7 +1130,7 @@ expand_epilogue (void)
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if (regs_ever_live[i] && ! call_used_regs[i])
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{
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rtx addr;
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if (reg)
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addr = reg;
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else if (size)
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@ -1167,7 +1167,7 @@ expand_epilogue (void)
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If the stack size + register save area is more than 255 bytes,
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then the stack must be cut back here since the size + register
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save size is too big for a ret/retf instruction.
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save size is too big for a ret/retf instruction.
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Else leave it alone, it will be cut back as part of the
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ret/retf instruction, or there wasn't any stack to begin with.
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@ -1333,7 +1333,7 @@ store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
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}
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/* What (if any) secondary registers are needed to move IN with mode
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MODE into a register in register class CLASS.
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MODE into a register in register class CLASS.
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We might be able to simplify this. */
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enum reg_class
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@ -1380,9 +1380,10 @@ mn10300_secondary_reload_class (enum reg_class class, enum machine_mode mode,
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return DATA_OR_EXTENDED_REGS;
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return DATA_REGS;
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}
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if (TARGET_AM33_2 && class == FP_REGS
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&& GET_CODE (in) == MEM && ! OK_FOR_Q (in))
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&& GET_CODE (in) == MEM
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&& ! (GET_CODE (in) == MEM && !CONSTANT_ADDRESS_P (XEXP (in, 0))))
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{
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if (TARGET_AM33)
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return DATA_OR_EXTENDED_REGS;
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@ -1426,11 +1427,11 @@ initial_offset (int from, int to)
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return (get_frame_size () + REG_SAVE_BYTES
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+ 4 * fp_regs_to_save ()
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+ (current_function_outgoing_args_size
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? current_function_outgoing_args_size + 4 : 0));
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? current_function_outgoing_args_size + 4 : 0));
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else
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return (get_frame_size ()
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+ (current_function_outgoing_args_size
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? current_function_outgoing_args_size + 4 : 0));
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? current_function_outgoing_args_size + 4 : 0));
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}
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/* The difference between the frame pointer and stack pointer is the sum
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@ -1439,7 +1440,7 @@ initial_offset (int from, int to)
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if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
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return (get_frame_size ()
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+ (current_function_outgoing_args_size
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? current_function_outgoing_args_size + 4 : 0));
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? current_function_outgoing_args_size + 4 : 0));
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gcc_unreachable ();
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}
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@ -1624,7 +1625,7 @@ mn10300_function_value (tree valtype, tree func, int outgoing)
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= gen_rtx_EXPR_LIST (VOIDmode,
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gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM),
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GEN_INT (0));
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XVECEXP (rv, 0, 1)
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= gen_rtx_EXPR_LIST (VOIDmode,
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gen_rtx_REG (mode, FIRST_DATA_REGNUM),
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@ -1672,7 +1673,7 @@ output_tst (rtx operand, rtx insn)
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}
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/* Are we setting a data register to zero (this does not win for
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address registers)?
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address registers)?
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If it's a call clobbered register, have we past a call?
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@ -1688,7 +1689,7 @@ output_tst (rtx operand, rtx insn)
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== REGNO_REG_CLASS (REGNO (operand)))
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&& REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
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&& REGNO (SET_DEST (set)) != REGNO (operand)
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&& (!past_call
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&& (!past_call
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|| !call_used_regs[REGNO (SET_DEST (set))]))
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{
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rtx xoperands[2];
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@ -1707,7 +1708,7 @@ output_tst (rtx operand, rtx insn)
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!= REGNO_REG_CLASS (REGNO (operand)))
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&& REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
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&& REGNO (SET_DEST (set)) != REGNO (operand)
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&& (!past_call
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&& (!past_call
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|| !call_used_regs[REGNO (SET_DEST (set))]))
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{
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rtx xoperands[2];
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@ -2087,7 +2088,7 @@ mn10300_wide_const_load_uses_clr (rtx operands[2])
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val[1] = INTVAL (high);
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}
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break;
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case CONST_DOUBLE:
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if (GET_MODE (operands[1]) == DFmode)
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{
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@ -2103,7 +2104,7 @@ mn10300_wide_const_load_uses_clr (rtx operands[2])
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val[1] = CONST_DOUBLE_HIGH (operands[1]);
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}
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break;
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default:
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return false;
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}
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@ -251,12 +251,12 @@ extern enum processor_type mn10300_processor;
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For any two classes, it is very desirable that there be another
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class that represents their union. */
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enum reg_class {
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NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,
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DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS,
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DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS,
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EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS,
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SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS,
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SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS,
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FP_REGS, FP_ACC_REGS,
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GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
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};
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@ -313,19 +313,6 @@ enum reg_class {
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#define INDEX_REG_CLASS DATA_OR_EXTENDED_REGS
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#define BASE_REG_CLASS SP_OR_ADDRESS_REGS
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/* Get reg_class from a letter such as appears in the machine description. */
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#define REG_CLASS_FROM_LETTER(C) \
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((C) == 'd' ? DATA_REGS : \
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(C) == 'a' ? ADDRESS_REGS : \
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(C) == 'y' ? SP_REGS : \
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! TARGET_AM33 ? NO_REGS : \
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(C) == 'x' ? EXTENDED_REGS : \
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! TARGET_AM33_2 ? NO_REGS : \
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(C) == 'f' ? FP_REGS : \
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(C) == 'A' ? FP_ACC_REGS : \
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NO_REGS)
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|
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/* Macros to check register numbers against specific register classes. */
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|
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/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
|
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|
|
@ -440,40 +427,11 @@ enum reg_class {
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loaded the register. */
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#define CLASS_CANNOT_CHANGE_SIZE FP_REGS
|
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|
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/* The letters I, J, K, L, M, N, O, P in a register constraint string
|
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can be used to stand for particular ranges of immediate operands.
|
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This macro defines what the ranges are.
|
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C is the letter, and VALUE is a constant value.
|
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Return 1 if VALUE is in the range specified by C. */
|
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/* Return 1 if VALUE is in the range specified. */
|
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|
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#define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100)
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#define INT_16_BITS(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000)
|
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|
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#define CONST_OK_FOR_I(VALUE) ((VALUE) == 0)
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#define CONST_OK_FOR_J(VALUE) ((VALUE) == 1)
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#define CONST_OK_FOR_K(VALUE) ((VALUE) == 2)
|
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#define CONST_OK_FOR_L(VALUE) ((VALUE) == 4)
|
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#define CONST_OK_FOR_M(VALUE) ((VALUE) == 3)
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#define CONST_OK_FOR_N(VALUE) ((VALUE) == 255 || (VALUE) == 65535)
|
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|
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#define CONST_OK_FOR_LETTER_P(VALUE, C) \
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((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \
|
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(C) == 'J' ? CONST_OK_FOR_J (VALUE) : \
|
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(C) == 'K' ? CONST_OK_FOR_K (VALUE) : \
|
||||
(C) == 'L' ? CONST_OK_FOR_L (VALUE) : \
|
||||
(C) == 'M' ? CONST_OK_FOR_M (VALUE) : \
|
||||
(C) == 'N' ? CONST_OK_FOR_N (VALUE) : 0)
|
||||
|
||||
|
||||
/* Similar, but for floating constants, and defining letters G and H.
|
||||
Here VALUE is the CONST_DOUBLE rtx itself.
|
||||
|
||||
`G' is a floating-point zero. */
|
||||
|
||||
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
|
||||
((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
|
||||
&& (VALUE) == CONST0_RTX (GET_MODE (VALUE))) : 0)
|
||||
|
||||
|
||||
/* Stack layout; function entry, exit and calling. */
|
||||
|
||||
|
|
@ -585,7 +543,7 @@ struct cum_arg {int nbytes; };
|
|||
NAMED is nonzero if this argument is a named parameter
|
||||
(otherwise it is an extra parameter matching an ellipsis). */
|
||||
|
||||
/* On the MN10300 all args are pushed. */
|
||||
/* On the MN10300 all args are pushed. */
|
||||
|
||||
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
|
||||
function_arg (&CUM, MODE, TYPE, NAMED)
|
||||
|
|
@ -676,42 +634,6 @@ struct cum_arg {int nbytes; };
|
|||
|
||||
#define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
|
||||
|
||||
/* Extra constraints. */
|
||||
|
||||
#define OK_FOR_Q(OP) \
|
||||
(GET_CODE (OP) == MEM && ! CONSTANT_ADDRESS_P (XEXP (OP, 0)))
|
||||
|
||||
#define OK_FOR_R(OP) \
|
||||
(GET_CODE (OP) == MEM \
|
||||
&& GET_MODE (OP) == QImode \
|
||||
&& (CONSTANT_ADDRESS_P (XEXP (OP, 0)) \
|
||||
|| (GET_CODE (XEXP (OP, 0)) == REG \
|
||||
&& REG_OK_FOR_BIT_BASE_P (XEXP (OP, 0)) \
|
||||
&& XEXP (OP, 0) != stack_pointer_rtx) \
|
||||
|| (GET_CODE (XEXP (OP, 0)) == PLUS \
|
||||
&& GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
|
||||
&& REG_OK_FOR_BIT_BASE_P (XEXP (XEXP (OP, 0), 0)) \
|
||||
&& XEXP (XEXP (OP, 0), 0) != stack_pointer_rtx \
|
||||
&& GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT \
|
||||
&& INT_8_BITS (INTVAL (XEXP (XEXP (OP, 0), 1))))))
|
||||
|
||||
#define OK_FOR_T(OP) \
|
||||
(GET_CODE (OP) == MEM \
|
||||
&& GET_MODE (OP) == QImode \
|
||||
&& (GET_CODE (XEXP (OP, 0)) == REG \
|
||||
&& REG_OK_FOR_BIT_BASE_P (XEXP (OP, 0)) \
|
||||
&& XEXP (OP, 0) != stack_pointer_rtx))
|
||||
|
||||
#define EXTRA_CONSTRAINT(OP, C) \
|
||||
((C) == 'R' ? OK_FOR_R (OP) \
|
||||
: (C) == 'Q' ? OK_FOR_Q (OP) \
|
||||
: (C) == 'S' && flag_pic \
|
||||
? GET_CODE (OP) == UNSPEC && (XINT (OP, 1) == UNSPEC_PLT \
|
||||
|| XINT (OP, 1) == UNSPEC_PIC) \
|
||||
: (C) == 'S' ? GET_CODE (OP) == SYMBOL_REF \
|
||||
: (C) == 'T' ? OK_FOR_T (OP) \
|
||||
: 0)
|
||||
|
||||
/* Maximum number of registers that can appear in a valid memory address. */
|
||||
|
||||
#define MAX_REGS_PER_ADDRESS 2
|
||||
|
|
@ -740,7 +662,7 @@ struct cum_arg {int nbytes; };
|
|||
function record_unscaled_index_insn_codes. */
|
||||
|
||||
/* Accept either REG or SUBREG where a register is valid. */
|
||||
|
||||
|
||||
#define RTX_OK_FOR_BASE_P(X, strict) \
|
||||
((REG_P (X) && REGNO_STRICT_OK_FOR_BASE_P (REGNO (X), \
|
||||
(strict))) \
|
||||
|
|
@ -754,7 +676,7 @@ do \
|
|||
if (legitimate_address_p ((MODE), (X), REG_STRICT)) \
|
||||
goto ADDR; \
|
||||
} \
|
||||
while (0)
|
||||
while (0)
|
||||
|
||||
|
||||
/* Try machine-dependent ways of modifying an illegitimate address
|
||||
|
|
|
|||
|
|
@ -49,6 +49,7 @@
|
|||
])
|
||||
|
||||
(include "predicates.md")
|
||||
(include "constraints.md")
|
||||
|
||||
;; ----------------------------------------------------------------------
|
||||
;; MOVE INSTRUCTIONS
|
||||
|
|
@ -516,7 +517,7 @@
|
|||
return \"mov %H1,%H0\;mov %L1,%L0\";
|
||||
else
|
||||
return \"mov %L1,%L0\;mov %H1,%H0\";
|
||||
|
||||
|
||||
}
|
||||
else if (GET_CODE (operands[1]) == MEM
|
||||
&& CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
|
||||
|
|
@ -727,7 +728,7 @@
|
|||
return \"mov %H1,%H0\;mov %L1,%L0\";
|
||||
else
|
||||
return \"mov %L1,%L0\;mov %H1,%H0\";
|
||||
|
||||
|
||||
}
|
||||
else if (GET_CODE (operands[1]) == MEM
|
||||
&& CONSTANT_ADDRESS_P (XEXP (operands[1], 0))
|
||||
|
|
@ -920,7 +921,7 @@
|
|||
src1_class = REGNO_REG_CLASS (true_regnum (operands[1]));
|
||||
src2_class = REGNO_REG_CLASS (true_regnum (operands[2]));
|
||||
dst_class = REGNO_REG_CLASS (true_regnum (operands[0]));
|
||||
|
||||
|
||||
/* I'm not sure if this can happen or not. Might as well be prepared
|
||||
and generate the best possible code if it does happen. */
|
||||
if (true_regnum (operands[0]) == true_regnum (operands[1]))
|
||||
|
|
@ -938,7 +939,7 @@
|
|||
add the other source to the destination.
|
||||
|
||||
Carefully select which source to copy to the destination; a naive
|
||||
implementation will waste a byte when the source classes are
|
||||
implementation will waste a byte when the source classes are
|
||||
different and the destination is an address register. Selecting
|
||||
the lowest cost register copy will optimize this sequence. */
|
||||
if (REGNO_REG_CLASS (true_regnum (operands[1]))
|
||||
|
|
@ -1119,7 +1120,7 @@
|
|||
return \"mul %2,%0\";
|
||||
}"
|
||||
[(set_attr "cc" "set_zn")])
|
||||
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "register_operand" "=dx")
|
||||
(mult:SI (match_operand:SI 1 "register_operand" "%0")
|
||||
|
|
@ -1561,7 +1562,7 @@
|
|||
else if (mask & 0xff000000)
|
||||
mask = (mask >> 24) & 0xff;
|
||||
}
|
||||
|
||||
|
||||
xoperands[0] = operands[0];
|
||||
xoperands[1] = GEN_INT (trunc_int_for_mode (mask, SImode));
|
||||
if (GET_CODE (operands[0]) == REG)
|
||||
|
|
@ -2462,7 +2463,7 @@
|
|||
return \"\";
|
||||
}"
|
||||
[(set_attr "cc" "clobber")])
|
||||
|
||||
|
||||
(define_insn "return"
|
||||
[(return)]
|
||||
"can_use_return_insn ()"
|
||||
|
|
|
|||
|
|
@ -44,7 +44,7 @@
|
|||
(match_code "symbol_ref,reg,unspec")
|
||||
{
|
||||
if (flag_pic)
|
||||
return (EXTRA_CONSTRAINT (op, 'S') || GET_CODE (op) == REG);
|
||||
return (satisfies_constraint_S (op) || GET_CODE (op) == REG);
|
||||
|
||||
return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
|
||||
})
|
||||
|
|
|
|||
|
|
@ -621,7 +621,7 @@ gen_split (rtx split)
|
|||
else
|
||||
{
|
||||
printf ("extern rtx gen_split_%d (rtx, rtx *);\n", insn_code_number);
|
||||
printf ("rtx\ngen_split_%d (rtx curr_insn ATTRIBUTE_UNUSED, rtx *operands%s)\n",
|
||||
printf ("rtx\ngen_split_%d (rtx curr_insn ATTRIBUTE_UNUSED, rtx *operands%s)\n",
|
||||
insn_code_number, unused);
|
||||
}
|
||||
printf ("{\n");
|
||||
|
|
@ -854,9 +854,10 @@ from the machine description file `md'. */\n\n");
|
|||
printf ("#include \"resource.h\"\n");
|
||||
printf ("#include \"reload.h\"\n");
|
||||
printf ("#include \"toplev.h\"\n");
|
||||
printf ("#include \"regs.h\"\n");
|
||||
printf ("#include \"tm-constrs.h\"\n");
|
||||
printf ("#include \"ggc.h\"\n\n");
|
||||
printf ("#include \"basic-block.h\"\n\n");
|
||||
printf ("#include \"ggc.h\"\n");
|
||||
printf ("#include \"basic-block.h\"\n");
|
||||
printf ("#include \"integrate.h\"\n\n");
|
||||
printf ("#define FAIL return (end_sequence (), _val)\n");
|
||||
printf ("#define DONE return (_val = get_insns (), end_sequence (), _val)\n\n");
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@ static int pattern_lineno;
|
|||
/* Count of errors. */
|
||||
static int error_count;
|
||||
|
||||
/* Predicate handling.
|
||||
/* Predicate handling.
|
||||
|
||||
We construct from the machine description a table mapping each
|
||||
predicate to a list of the rtl codes it can possibly match. The
|
||||
|
|
@ -259,7 +259,7 @@ compute_predicate_codes (rtx exp, char codes[NUM_RTX_CODE])
|
|||
break;
|
||||
|
||||
case IF_THEN_ELSE:
|
||||
/* a ? b : c accepts the same codes as (a & b) | (!a & c). */
|
||||
/* a ? b : c accepts the same codes as (a & b) | (!a & c). */
|
||||
compute_predicate_codes (XEXP (exp, 0), op0_codes);
|
||||
compute_predicate_codes (XEXP (exp, 1), op1_codes);
|
||||
compute_predicate_codes (XEXP (exp, 2), op2_codes);
|
||||
|
|
@ -295,7 +295,7 @@ compute_predicate_codes (rtx exp, char codes[NUM_RTX_CODE])
|
|||
{
|
||||
size_t n = next_code - code;
|
||||
int found_it = 0;
|
||||
|
||||
|
||||
for (i = 0; i < NUM_RTX_CODE; i++)
|
||||
if (!strncmp (code, GET_RTX_NAME (i), n)
|
||||
&& GET_RTX_NAME (i)[n] == '\0')
|
||||
|
|
@ -1088,7 +1088,7 @@ add_to_sequence (rtx pattern, struct decision_head *last, const char *position,
|
|||
if (fmt[i] == 'i')
|
||||
{
|
||||
gcc_assert (i < 2);
|
||||
|
||||
|
||||
if (!i)
|
||||
{
|
||||
test = new_decision_test (DT_elt_zero_int, &place);
|
||||
|
|
@ -2496,6 +2496,7 @@ write_header (void)
|
|||
#include \"resource.h\"\n\
|
||||
#include \"toplev.h\"\n\
|
||||
#include \"reload.h\"\n\
|
||||
#include \"regs.h\"\n\
|
||||
#include \"tm-constrs.h\"\n\
|
||||
\n");
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue