mips-protos.h (mips_subword, [...]): Declare.
* config/mips/mips-protos.h (mips_subword, mips_output_move): Declare. (mips_move_1word, mips_move_2words): Remove declaration. (mips_split_64bit_move_p, mips_split_64bit_move): Declare. (mips_restore_gp): Remove insn argument. * config/mips/mips.h (FP_REG_RTX_P): New macro. * config/mips/mips.c (volatile_buffer): Remove. (mips_subword, mips_split_64bit_move_p, mips_split_64bit_move): New. (mips_move_1word, mips_move_2words): Remove, replacing with... (mips_output_move): ...this new function. (mips_restore_gp): Remove insn argument. Adjust for above changes. (print_operand): Make '%h' print %hi(op) for HIGH operands. Remove handling of floating-point constants. Handle zero CONST_DOUBLE arguments. (mips_annotate_frame_insn): Replace with... (mips_set_frame_expr): ...this, which just takes one argument. (mips_frame_set): Change the register argument to an rtx. (mips_emit_frame_related_store): Use mips_split_64bit_move_p to check whether moves should be split. Use mips_split_64bit_move to split them. Use mips_subword to generate the high and low parts of a paired FPR. Adjust calls to frame_set and mips_set_frame_expr. (mips_expand_prologue): Simplify due to above changes. * config/mips/mips.md: Add splitters for 64-bit moves on 32-bit targets, replacing xisting register-only versions. (UNSPEC_STORE_DF_HIGH): New unspec. (UNSPEC_LOAD_DF_LOW, UNSPEC_LOAD_DF_HIGH): New unspecs. (mulsi3_r4000, muldi3_internal2): Avoid use of mips_move_1word. (*paradoxical_extendhidi2): Remove. (movdi_internal, movdi_internal2): Use mips_output_move. (*movdi_internal2_mips16, movsi_internal, movcc): Likewise. (movsf_internal1, movsf_internal2): Likewise. (movdf_internal1a): Likewise. Fix length and type of f <- G case. (movdf_internal1b): Use mips_output_move. Fix type of f <- G case. (movdf_internal2): Use mips_output_move. Fix lengths of FPR moves. Add m <- G alternative. (load_df_low, load_df_high, store_df_low): New patterns. (movhi_internal): Use @ template instead of calling a function. Remove unnecessary 'z' alternatives. (movqi_internal): Likewise. (exception_receiver): Update call to mips_restore_gp. From-SVN: r66521
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
83f564f76f
commit
5b0f0db6d9
@ -1,3 +1,46 @@
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2003-05-06 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips-protos.h (mips_subword, mips_output_move): Declare.
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(mips_move_1word, mips_move_2words): Remove declaration.
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(mips_split_64bit_move_p, mips_split_64bit_move): Declare.
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(mips_restore_gp): Remove insn argument.
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* config/mips/mips.h (FP_REG_RTX_P): New macro.
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* config/mips/mips.c (volatile_buffer): Remove.
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(mips_subword, mips_split_64bit_move_p, mips_split_64bit_move): New.
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(mips_move_1word, mips_move_2words): Remove, replacing with...
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(mips_output_move): ...this new function.
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(mips_restore_gp): Remove insn argument. Adjust for above changes.
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(print_operand): Make '%h' print %hi(op) for HIGH operands. Remove
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handling of floating-point constants. Handle zero CONST_DOUBLE
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arguments.
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(mips_annotate_frame_insn): Replace with...
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(mips_set_frame_expr): ...this, which just takes one argument.
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(mips_frame_set): Change the register argument to an rtx.
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(mips_emit_frame_related_store): Use mips_split_64bit_move_p to
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check whether moves should be split. Use mips_split_64bit_move
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to split them. Use mips_subword to generate the high and low
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parts of a paired FPR. Adjust calls to frame_set and
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mips_set_frame_expr.
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(mips_expand_prologue): Simplify due to above changes.
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* config/mips/mips.md: Add splitters for 64-bit moves on 32-bit
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targets, replacing xisting register-only versions.
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(UNSPEC_STORE_DF_HIGH): New unspec.
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(UNSPEC_LOAD_DF_LOW, UNSPEC_LOAD_DF_HIGH): New unspecs.
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(mulsi3_r4000, muldi3_internal2): Avoid use of mips_move_1word.
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(*paradoxical_extendhidi2): Remove.
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(movdi_internal, movdi_internal2): Use mips_output_move.
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(*movdi_internal2_mips16, movsi_internal, movcc): Likewise.
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(movsf_internal1, movsf_internal2): Likewise.
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(movdf_internal1a): Likewise. Fix length and type of f <- G case.
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(movdf_internal1b): Use mips_output_move. Fix type of f <- G case.
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(movdf_internal2): Use mips_output_move. Fix lengths of FPR moves.
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Add m <- G alternative.
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(load_df_low, load_df_high, store_df_low): New patterns.
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(movhi_internal): Use @ template instead of calling a function.
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Remove unnecessary 'z' alternatives.
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(movqi_internal): Likewise.
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(exception_receiver): Update call to mips_restore_gp.
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2003-05-06 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips-protos.h (mips_simplify_dwarf_addr): Remove.
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@ -100,10 +100,12 @@ extern HOST_WIDE_INT mips_debugger_offset PARAMS ((rtx, HOST_WIDE_INT));
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extern const char *mips_fill_delay_slot PARAMS ((const char *,
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enum delay_type, rtx *,
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rtx));
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extern const char *mips_move_1word PARAMS ((rtx *, rtx, int));
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extern const char *mips_move_2words PARAMS ((rtx *, rtx));
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extern rtx mips_subword PARAMS ((rtx, int));
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extern bool mips_split_64bit_move_p PARAMS ((rtx, rtx));
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extern void mips_split_64bit_move PARAMS ((rtx, rtx));
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extern const char *mips_output_move PARAMS ((rtx, rtx));
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extern const char *mips_emit_prefetch PARAMS ((rtx *));
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extern const char *mips_restore_gp PARAMS ((rtx *, rtx));
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extern const char *mips_restore_gp PARAMS ((rtx *));
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extern const char *output_block_move PARAMS ((rtx, rtx *, int,
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enum block_move_type));
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extern void override_options PARAMS ((void));
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File diff suppressed because it is too large
Load Diff
@ -1935,6 +1935,8 @@ do { \
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#define ALL_COP_REG_P(REGNO) \
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((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
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#define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
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/* Return coprocessor number from register number. */
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#define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
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@ -27,7 +27,10 @@
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;; Must include new entries for fmadd in addition to existing entries.
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(define_constants
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[(UNSPEC_GET_FNADDR 4)
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[(UNSPEC_LOAD_DF_LOW 0)
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(UNSPEC_LOAD_DF_HIGH 1)
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(UNSPEC_STORE_DF_HIGH 2)
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(UNSPEC_GET_FNADDR 4)
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(UNSPEC_HILO_DELAY 5)
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(UNSPEC_BLOCKAGE 6)
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(UNSPEC_LOADGP 7)
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@ -1920,20 +1923,10 @@
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(clobber (match_scratch:SI 4 "=l"))
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(clobber (match_scratch:SI 5 "=a"))]
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"TARGET_MIPS4000 && !TARGET_MIPS16"
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"*
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{
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rtx xoperands[10];
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xoperands[0] = operands[0];
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xoperands[1] = gen_rtx_REG (SImode, LO_REGNUM);
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output_asm_insn (\"mult\\t%1,%2\", operands);
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output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
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return \"\";
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}"
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"mult\t%1,%2\;mflo\t%0"
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[(set_attr "type" "imul")
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(set_attr "mode" "SI")
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(set_attr "length" "12")]) ;; mult + mflo + delay
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(set_attr "length" "8")])
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;; Multiply-accumulate patterns
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@ -2307,28 +2300,18 @@
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(clobber (match_scratch:DI 4 "=l"))
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(clobber (match_scratch:DI 5 "=a"))]
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"TARGET_64BIT && (GENERATE_MULT3_DI || TARGET_MIPS4000 || TARGET_MIPS16)"
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"*
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{
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if (GENERATE_MULT3_DI)
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output_asm_insn (\"dmult\\t%0,%1,%2\", operands);
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else
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{
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rtx xoperands[10];
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xoperands[0] = operands[0];
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xoperands[1] = gen_rtx_REG (DImode, LO_REGNUM);
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output_asm_insn (\"dmult\\t%1,%2\", operands);
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output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
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}
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return \"\";
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}"
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{
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if (GENERATE_MULT3_DI)
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return "dmult\t%0,%1,%2";
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else
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return "dmult\t%1,%2\n\tmflo\t%0";
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}
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[(set_attr "type" "imul")
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(set_attr "mode" "DI")
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(set (attr "length")
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(if_then_else (ne (symbol_ref "GENERATE_MULT3_DI") (const_int 0))
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(const_int 4)
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(const_int 12)))]) ;; mult + mflo + delay
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(const_int 4)
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(const_int 8)))])
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;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
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@ -4300,23 +4283,6 @@ move\\t%0,%z4\\n\\
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(set_attr "mode" "DI")
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(set_attr "length" "4,*")])
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;; These can be created when a paradoxical subreg operand with an implicit
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;; sign_extend operator is reloaded. Because of the subreg, this is really
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;; a zero extend.
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;; ??? It might be possible to eliminate the need for these patterns by adding
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;; more support to reload for implicit sign_extend operators.
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(define_insn "*paradoxical_extendhidi2"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(sign_extend:DI
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(subreg:SI (match_operand:HI 1 "memory_operand" "m") 0)))]
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"TARGET_64BIT"
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"*
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{
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return mips_move_1word (operands, insn, TRUE);
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}"
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[(set_attr "type" "load")
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(set_attr "mode" "DI")])
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=d")
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(zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
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@ -5114,11 +5080,7 @@ move\\t%0,%z4\\n\\
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[(set (match_operand:DI 0 "memory_operand" "=m")
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(reg:DI 31))]
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"TARGET_MIPS16 && TARGET_64BIT"
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"*
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{
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operands[1] = gen_rtx (REG, DImode, 31);
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return mips_move_2words (operands, insn);
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}"
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"sd\t$31,%0"
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[(set_attr "type" "store")
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(set_attr "mode" "DI")])
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@ -5130,7 +5092,7 @@ move\\t%0,%z4\\n\\
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|| register_operand (operands[1], DImode)
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|| (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
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|| operands[1] == CONST0_RTX (DImode))"
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"* return mips_move_2words (operands, insn); "
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{ return mips_output_move (operands[0], operands[1]); }
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[(set_attr "type" "move,arith,load,store,hilo,hilo,hilo,xfer,load,xfer,store")
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(set_attr "mode" "DI")
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(set_attr "length" "8,16,*,*,8,8,8,8,*,8,*")])
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@ -5141,23 +5103,11 @@ move\\t%0,%z4\\n\\
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"!TARGET_64BIT && TARGET_MIPS16
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&& (register_operand (operands[0], DImode)
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|| register_operand (operands[1], DImode))"
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"* return mips_move_2words (operands, insn);"
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{ return mips_output_move (operands[0], operands[1]); }
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[(set_attr "type" "move,move,move,arith,arith,load,store,hilo")
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(set_attr "mode" "DI")
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(set_attr "length" "8,8,8,8,12,*,*,8")])
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(define_split
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[(set (match_operand:DI 0 "register_operand" "")
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(match_operand:DI 1 "register_operand" ""))]
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"reload_completed && !TARGET_64BIT
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&& !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
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&& GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
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&& GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
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[(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
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(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
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"")
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(define_insn "movdi_internal2"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*d,*x,*a,*B*C*D,*B*C*D,*d,*m")
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(match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J,*x,*d,*J,*d,*m,*B*C*D,*B*C*D"))]
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@ -5166,31 +5116,18 @@ move\\t%0,%z4\\n\\
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|| register_operand (operands[1], DImode)
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|| (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
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|| operands[1] == CONST0_RTX (DImode))"
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"* return mips_move_2words (operands, insn); "
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{ return mips_output_move (operands[0], operands[1]); }
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[(set_attr "type" "move,const,const,load,store,move,xfer,load,xfer,store,hilo,hilo,hilo,hilo,xfer,load,xfer,store")
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(set_attr "mode" "DI")
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(set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,8,8,*,8,*")])
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;; Sign-extended operands are reloaded using this instruction, so the
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;; constraints must handle every SImode source operand X and destination
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;; register R for which:
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;;
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;; mips_secondary_reload_class (CLASS_OF (R), DImode, true,
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;; gen_rtx_SIGN_EXTEND (DImode, X))
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;;
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;; returns NO_REGS. Also handle memory destinations, where allowed.
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;;
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;; This pattern is essentially a trimmed-down version of movdi_internal2.
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;; The main difference is that dJ -> f and f -> d are the only constraints
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;; involving float registers. See mips_secondary_reload_class for details.
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(define_insn "*movdi_internal2_mips16"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m,*d")
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(match_operand:DI 1 "move_operand" "d,d,y,K,N,U,m,d,*x"))]
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"TARGET_64BIT && TARGET_MIPS16
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&& (register_operand (operands[0], DImode)
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|| register_operand (operands[1], DImode))"
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"* return mips_move_2words (operands, insn);"
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{ return mips_output_move (operands[0], operands[1]); }
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[(set_attr "type" "move,move,move,arith,arith,const,load,store,hilo")
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(set_attr "mode" "DI")
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(set_attr_alternative "length"
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@ -5478,7 +5415,7 @@ move\\t%0,%z4\\n\\
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&& (register_operand (operands[0], SImode)
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|| register_operand (operands[1], SImode)
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|| (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
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"* return mips_move_1word (operands, insn, FALSE);"
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{ return mips_output_move (operands[0], operands[1]); }
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[(set_attr "type" "move,const,const,load,store,move,xfer,load,xfer,store,xfer,xfer,hilo,hilo,hilo,hilo,xfer,load,xfer,store")
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(set_attr "mode" "SI")
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(set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,4,4,4,*,4,*")])
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@ -5489,7 +5426,7 @@ move\\t%0,%z4\\n\\
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"TARGET_MIPS16
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&& (register_operand (operands[0], SImode)
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|| register_operand (operands[1], SImode))"
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"* return mips_move_1word (operands, insn, FALSE);"
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{ return mips_output_move (operands[0], operands[1]); }
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[(set_attr "type" "move,move,move,arith,arith,const,load,store,hilo,hilo")
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(set_attr "mode" "SI")
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(set_attr_alternative "length"
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@ -5575,7 +5512,7 @@ move\\t%0,%z4\\n\\
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}")
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;; On the mips16, we can split a load of a negative constant into a
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;; load and a neg. That's what mips_move_1word will generate anyhow.
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;; load and a neg. That's what mips_output_move will generate anyhow.
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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@ -5753,7 +5690,7 @@ move\\t%0,%z4\\n\\
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[(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
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(match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
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"ISA_HAS_8CC && TARGET_HARD_FLOAT"
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"* return mips_move_1word (operands, insn, FALSE);"
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{ return mips_output_move (operands[0], operands[1]); }
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[(set_attr "type" "move,move,load,store,xfer,xfer,move,load,store")
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(set_attr "mode" "SI")
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(set_attr "length" "8,4,*,*,4,4,4,*,*")])
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@ -5917,13 +5854,22 @@ move\\t%0,%z4\\n\\
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;; in FP registers (off by default, use -mdebugh to enable).
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(define_insn "movhi_internal"
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[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f*z,*f,*x,*d")
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(match_operand:HI 1 "general_operand" "d,IK,m,dJ,*f*z,*d,*f,*d,*x"))]
|
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[(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x,*d")
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(match_operand:HI 1 "general_operand" "d,IK,m,dJ,*f,*d,*f,*d,*x"))]
|
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"!TARGET_MIPS16
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||||
&& (register_operand (operands[0], HImode)
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|| register_operand (operands[1], HImode)
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|| (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
|
||||
"* return mips_move_1word (operands, insn, TRUE);"
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"@
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||||
move\t%0,%1
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li\t%0,%1
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lhu\t%0,%1
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||||
sh\t%z1,%0
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||||
mfc1\t%0,%1
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||||
mtc1\t%1,%0
|
||||
mov.s\t%0,%1
|
||||
mt%0\t%1
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||||
mf%1\t%0"
|
||||
[(set_attr "type" "move,arith,load,store,xfer,xfer,move,hilo,hilo")
|
||||
(set_attr "mode" "HI")
|
||||
(set_attr "length" "4,4,*,*,4,4,4,4,4")])
|
||||
@ -5934,7 +5880,15 @@ move\\t%0,%z4\\n\\
|
||||
"TARGET_MIPS16
|
||||
&& (register_operand (operands[0], HImode)
|
||||
|| register_operand (operands[1], HImode))"
|
||||
"* return mips_move_1word (operands, insn, TRUE);"
|
||||
"@
|
||||
move\t%0,%1
|
||||
move\t%0,%1
|
||||
move\t%0,%1
|
||||
li\t%0,%1
|
||||
li\t%0,%n1\;neg\t%0
|
||||
lhu\t%0,%1
|
||||
sh\t%1,%0
|
||||
mf%1\t%0"
|
||||
[(set_attr "type" "move,move,move,arith,arith,load,store,hilo")
|
||||
(set_attr "mode" "HI")
|
||||
(set_attr_alternative "length"
|
||||
@ -6025,13 +5979,22 @@ move\\t%0,%z4\\n\\
|
||||
;; in FP registers (off by default, use -mdebugh to enable).
|
||||
|
||||
(define_insn "movqi_internal"
|
||||
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f*z,*f,*x,*d")
|
||||
(match_operand:QI 1 "general_operand" "d,IK,m,dJ,*f*z,*d,*f,*d,*x"))]
|
||||
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x,*d")
|
||||
(match_operand:QI 1 "general_operand" "d,IK,m,dJ,*f,*d,*f,*d,*x"))]
|
||||
"!TARGET_MIPS16
|
||||
&& (register_operand (operands[0], QImode)
|
||||
|| register_operand (operands[1], QImode)
|
||||
|| (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
|
||||
"* return mips_move_1word (operands, insn, TRUE);"
|
||||
"@
|
||||
move\t%0,%1
|
||||
li\t%0,%1
|
||||
lbu\t%0,%1
|
||||
sb\t%z1,%0
|
||||
mfc1\t%0,%1
|
||||
mtc1\t%1,%0
|
||||
mov.s\t%0,%1
|
||||
mt%0\t%1
|
||||
mf%1\t%0"
|
||||
[(set_attr "type" "move,arith,load,store,xfer,xfer,move,hilo,hilo")
|
||||
(set_attr "mode" "QI")
|
||||
(set_attr "length" "4,4,*,*,4,4,4,4,4")])
|
||||
@ -6042,23 +6005,18 @@ move\\t%0,%z4\\n\\
|
||||
"TARGET_MIPS16
|
||||
&& (register_operand (operands[0], QImode)
|
||||
|| register_operand (operands[1], QImode))"
|
||||
"* return mips_move_1word (operands, insn, TRUE);"
|
||||
"@
|
||||
move\t%0,%1
|
||||
move\t%0,%1
|
||||
move\t%0,%1
|
||||
li\t%0,%1
|
||||
li\t%0,%n1\;neg\t%0
|
||||
lbu\t%0,%1
|
||||
sb\t%1,%0
|
||||
mf%1\t%0"
|
||||
[(set_attr "type" "move,move,move,arith,arith,load,store,hilo")
|
||||
(set_attr "mode" "QI")
|
||||
(set_attr_alternative "length"
|
||||
[(const_int 4)
|
||||
(const_int 4)
|
||||
(const_int 4)
|
||||
(if_then_else (match_operand:VOID 1 "m16_uimm8_1" "")
|
||||
(const_int 4)
|
||||
(const_int 8))
|
||||
(if_then_else (match_operand:VOID 1 "m16_nuimm8_1" "")
|
||||
(const_int 8)
|
||||
(const_int 12))
|
||||
(const_string "*")
|
||||
(const_string "*")
|
||||
(const_int 4)])])
|
||||
|
||||
(set_attr "length" "4,4,4,4,8,*,*,4")])
|
||||
|
||||
;; On the mips16, we can split lb $r,N($r) into an add and a load,
|
||||
;; when the original load is a 4 byte instruction but the add and the
|
||||
@ -6111,7 +6069,7 @@ move\\t%0,%z4\\n\\
|
||||
"TARGET_HARD_FLOAT
|
||||
&& (register_operand (operands[0], SFmode)
|
||||
|| nonmemory_operand (operands[1], SFmode))"
|
||||
"* return mips_move_1word (operands, insn, FALSE);"
|
||||
{ return mips_output_move (operands[0], operands[1]); }
|
||||
[(set_attr "type" "move,xfer,load,store,xfer,xfer,move,load,store")
|
||||
(set_attr "mode" "SF")
|
||||
(set_attr "length" "4,4,*,*,4,4,4,*,*")])
|
||||
@ -6122,7 +6080,7 @@ move\\t%0,%z4\\n\\
|
||||
"TARGET_SOFT_FLOAT && !TARGET_MIPS16
|
||||
&& (register_operand (operands[0], SFmode)
|
||||
|| nonmemory_operand (operands[1], SFmode))"
|
||||
"* return mips_move_1word (operands, insn, FALSE);"
|
||||
{ return mips_output_move (operands[0], operands[1]); }
|
||||
[(set_attr "type" "move,load,store")
|
||||
(set_attr "mode" "SF")
|
||||
(set_attr "length" "4,*,*")])
|
||||
@ -6133,7 +6091,7 @@ move\\t%0,%z4\\n\\
|
||||
"TARGET_MIPS16
|
||||
&& (register_operand (operands[0], SFmode)
|
||||
|| register_operand (operands[1], SFmode))"
|
||||
"* return mips_move_1word (operands, insn, FALSE);"
|
||||
{ return mips_output_move (operands[0], operands[1]); }
|
||||
[(set_attr "type" "move,move,move,load,store")
|
||||
(set_attr "mode" "SF")
|
||||
(set_attr "length" "4,4,4,*,*")])
|
||||
@ -6159,10 +6117,10 @@ move\\t%0,%z4\\n\\
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
|
||||
&& (register_operand (operands[0], DFmode)
|
||||
|| nonmemory_operand (operands[1], DFmode))"
|
||||
"* return mips_move_2words (operands, insn); "
|
||||
[(set_attr "type" "move,move,load,store,xfer,xfer,move,load,store")
|
||||
{ return mips_output_move (operands[0], operands[1]); }
|
||||
[(set_attr "type" "move,xfer,load,store,xfer,xfer,move,load,store")
|
||||
(set_attr "mode" "DF")
|
||||
(set_attr "length" "4,8,*,*,4,4,4,*,*")])
|
||||
(set_attr "length" "4,4,*,*,4,4,4,*,*")])
|
||||
|
||||
(define_insn "movdf_internal1b"
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
|
||||
@ -6170,21 +6128,21 @@ move\\t%0,%z4\\n\\
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
|
||||
&& (register_operand (operands[0], DFmode)
|
||||
|| nonmemory_operand (operands[1], DFmode))"
|
||||
"* return mips_move_2words (operands, insn); "
|
||||
[(set_attr "type" "move,move,load,store,xfer,xfer,move,load,store")
|
||||
{ return mips_output_move (operands[0], operands[1]); }
|
||||
[(set_attr "type" "move,xfer,load,store,xfer,xfer,move,load,store")
|
||||
(set_attr "mode" "DF")
|
||||
(set_attr "length" "4,8,*,*,8,8,8,*,*")])
|
||||
|
||||
(define_insn "movdf_internal2"
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
|
||||
(match_operand:DF 1 "general_operand" "dG,m,d,f,d,f"))]
|
||||
(match_operand:DF 1 "general_operand" "dG,m,dG,f,d,f"))]
|
||||
"(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
|
||||
&& (register_operand (operands[0], DFmode)
|
||||
|| nonmemory_operand (operands[1], DFmode))"
|
||||
"* return mips_move_2words (operands, insn); "
|
||||
{ return mips_output_move (operands[0], operands[1]); }
|
||||
[(set_attr "type" "move,load,store,xfer,xfer,move")
|
||||
(set_attr "mode" "DF")
|
||||
(set_attr "length" "8,*,*,8,8,4")])
|
||||
(set_attr "length" "8,*,*,4,4,4")])
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
|
||||
@ -6192,21 +6150,81 @@ move\\t%0,%z4\\n\\
|
||||
"TARGET_MIPS16
|
||||
&& (register_operand (operands[0], DFmode)
|
||||
|| register_operand (operands[1], DFmode))"
|
||||
"* return mips_move_2words (operands, insn);"
|
||||
{ return mips_output_move (operands[0], operands[1]); }
|
||||
[(set_attr "type" "move,move,move,load,store")
|
||||
(set_attr "mode" "DF")
|
||||
(set_attr "length" "8,8,8,*,*")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DF 0 "register_operand" "")
|
||||
(match_operand:DF 1 "register_operand" ""))]
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "")
|
||||
(match_operand:DI 1 "general_operand" ""))]
|
||||
"reload_completed && !TARGET_64BIT
|
||||
&& !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
|
||||
&& GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
|
||||
&& GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
|
||||
[(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
|
||||
(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
|
||||
"")
|
||||
&& mips_split_64bit_move_p (operands[0], operands[1])"
|
||||
[(const_int 0)]
|
||||
{
|
||||
mips_split_64bit_move (operands[0], operands[1]);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "")
|
||||
(match_operand:DF 1 "general_operand" ""))]
|
||||
"reload_completed && !TARGET_64BIT
|
||||
&& mips_split_64bit_move_p (operands[0], operands[1])"
|
||||
[(const_int 0)]
|
||||
{
|
||||
mips_split_64bit_move (operands[0], operands[1]);
|
||||
DONE;
|
||||
})
|
||||
|
||||
;; Patterns for loading or storing part of a paired floating point
|
||||
;; register. We need them because odd-numbered floating-point registers
|
||||
;; are not fully independent: see mips_split_64bit_move.
|
||||
|
||||
;; Load the low word of operand 0 with operand 1.
|
||||
(define_insn "load_df_low"
|
||||
[(set (match_operand:DF 0 "register_operand" "=f,f")
|
||||
(unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
|
||||
UNSPEC_LOAD_DF_LOW))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
|
||||
{
|
||||
operands[0] = mips_subword (operands[0], 0);
|
||||
return mips_output_move (operands[0], operands[1]);
|
||||
}
|
||||
[(set_attr "type" "xfer,load")
|
||||
(set_attr "mode" "SF")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
;; Load the high word of operand 0 from operand 1, preserving the value
|
||||
;; in the low word.
|
||||
(define_insn "load_df_high"
|
||||
[(set (match_operand:DF 0 "register_operand" "=f,f")
|
||||
(unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")
|
||||
(match_operand:DF 2 "register_operand" "0,0")]
|
||||
UNSPEC_LOAD_DF_HIGH))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
|
||||
{
|
||||
operands[0] = mips_subword (operands[0], 1);
|
||||
return mips_output_move (operands[0], operands[1]);
|
||||
}
|
||||
[(set_attr "type" "xfer,load")
|
||||
(set_attr "mode" "SF")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
;; Store the high word of operand 1 in operand 0. The corresponding
|
||||
;; low-word move is done in the normal way.
|
||||
(define_insn "store_df_high"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
|
||||
(unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
|
||||
UNSPEC_STORE_DF_HIGH))]
|
||||
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
|
||||
{
|
||||
operands[1] = mips_subword (operands[1], 1);
|
||||
return mips_output_move (operands[0], operands[1]);
|
||||
}
|
||||
[(set_attr "type" "xfer,store")
|
||||
(set_attr "mode" "SF")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
;; Instructions to load the global pointer register.
|
||||
;; This is volatile to make sure that the scheduler won't move any symbol_ref
|
||||
@ -9808,7 +9826,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2"
|
||||
(define_insn "exception_receiver"
|
||||
[(unspec_volatile [(const_int 0)] UNSPEC_EH_RECEIVER)]
|
||||
"TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64)"
|
||||
"* return mips_restore_gp (operands, insn);"
|
||||
{ return mips_restore_gp (operands); }
|
||||
[(set_attr "type" "load")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user