Auto-vectorizer generates 128-bit AVX insns by default for bdver1.
* config/i386/i386.opt (mprefer-avx128): Redefine the flag as a Mask option. * config/i386/i386.h (ix86_tune_indices): Add X86_TUNE_AVX128_OPTIMAL entry. (TARGET_AVX128_OPTIMAL): New definition. * config/i386/i386.c (initial_ix86_tune_features): Initialize X86_TUNE_AVX128_OPTIMAL entry. (ix86_option_override_internal): Enable the generation of the 128-bit instructions when TARGET_AVX128_OPTIMAL is set. (ix86_preferred_simd_mode): Use TARGET_PREFER_AVX128. (ix86_autovectorize_vector_sizes): Use TARGET_PREFER_AVX128. From-SVN: r175661
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@ -1,3 +1,15 @@
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2011-06-29 Changpeng Fang <changpeng.fang@amd.com>
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* config/i386/i386.opt (mprefer-avx128): Redefine the flag as a Mask option.
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* config/i386/i386.h (ix86_tune_indices): Add X86_TUNE_AVX128_OPTIMAL entry.
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(TARGET_AVX128_OPTIMAL): New definition.
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* config/i386/i386.c (initial_ix86_tune_features): Initialize
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X86_TUNE_AVX128_OPTIMAL entry.
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(ix86_option_override_internal): Enable the generation
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of the 128-bit instructions when TARGET_AVX128_OPTIMAL is set.
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(ix86_preferred_simd_mode): Use TARGET_PREFER_AVX128.
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(ix86_autovectorize_vector_sizes): Use TARGET_PREFER_AVX128.
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2011-06-29 Eric Botcazou <ebotcazou@adacore.com>
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PR tree-optimization/49539
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@ -2089,7 +2089,11 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
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/* X86_SOFTARE_PREFETCHING_BENEFICIAL: Enable software prefetching
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at -O3. For the moment, the prefetching seems badly tuned for Intel
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chips. */
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m_K6_GEODE | m_AMD_MULTIPLE
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m_K6_GEODE | m_AMD_MULTIPLE,
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/* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
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the auto-vectorizer. */
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m_BDVER1
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};
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/* Feature tests against the various architecture variations. */
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@ -2623,6 +2627,7 @@ ix86_target_string (int isa, int flags, const char *arch, const char *tune,
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{ "-mvzeroupper", MASK_VZEROUPPER },
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{ "-mavx256-split-unaligned-load", MASK_AVX256_SPLIT_UNALIGNED_LOAD},
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{ "-mavx256-split-unaligned-store", MASK_AVX256_SPLIT_UNALIGNED_STORE},
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{ "-mprefer-avx128", MASK_PREFER_AVX128},
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};
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const char *opts[ARRAY_SIZE (isa_opts) + ARRAY_SIZE (flag_opts) + 6][2];
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@ -3672,6 +3677,9 @@ ix86_option_override_internal (bool main_args_p)
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if ((x86_avx256_split_unaligned_store & ix86_tune_mask)
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&& !(target_flags_explicit & MASK_AVX256_SPLIT_UNALIGNED_STORE))
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target_flags |= MASK_AVX256_SPLIT_UNALIGNED_STORE;
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/* Enable 128-bit AVX instruction generation for the auto-vectorizer. */
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if (TARGET_AVX128_OPTIMAL && !(target_flags_explicit & MASK_PREFER_AVX128))
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target_flags |= MASK_PREFER_AVX128;
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}
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}
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else
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@ -34614,7 +34622,7 @@ ix86_preferred_simd_mode (enum machine_mode mode)
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return V2DImode;
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case SFmode:
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if (TARGET_AVX && !flag_prefer_avx128)
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if (TARGET_AVX && !TARGET_PREFER_AVX128)
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return V8SFmode;
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else
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return V4SFmode;
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@ -34622,7 +34630,7 @@ ix86_preferred_simd_mode (enum machine_mode mode)
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case DFmode:
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if (!TARGET_VECTORIZE_DOUBLE)
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return word_mode;
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else if (TARGET_AVX && !flag_prefer_avx128)
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else if (TARGET_AVX && !TARGET_PREFER_AVX128)
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return V4DFmode;
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else if (TARGET_SSE2)
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return V2DFmode;
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@ -34639,7 +34647,7 @@ ix86_preferred_simd_mode (enum machine_mode mode)
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static unsigned int
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ix86_autovectorize_vector_sizes (void)
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{
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return (TARGET_AVX && !flag_prefer_avx128) ? 32 | 16 : 0;
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return (TARGET_AVX && !TARGET_PREFER_AVX128) ? 32 | 16 : 0;
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}
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/* Initialize the GCC target structure. */
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@ -312,6 +312,7 @@ enum ix86_tune_indices {
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X86_TUNE_OPT_AGU,
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X86_TUNE_VECTORIZE_DOUBLE,
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X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL,
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X86_TUNE_AVX128_OPTIMAL,
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X86_TUNE_LAST
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};
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@ -410,7 +411,8 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST];
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ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE]
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#define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \
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ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL]
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#define TARGET_AVX128_OPTIMAL \
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ix86_tune_features[X86_TUNE_AVX128_OPTIMAL]
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/* Feature tests against the various architecture variations. */
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enum ix86_arch_indices {
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X86_ARCH_CMOVE, /* || TARGET_SSE */
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@ -388,7 +388,7 @@ Do dispatch scheduling if processor is bdver1 and Haifa scheduling
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is selected.
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mprefer-avx128
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Target Report Var(flag_prefer_avx128) Init(0)
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Target Report Mask(PREFER_AVX128) SAVE
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Use 128-bit AVX instructions instead of 256-bit AVX instructions in the auto-vectorizer.
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;; ISA support
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