(extendsfdf2): SFmode and DFmode register format identical so use define_expand...
(extendsfdf2): SFmode and DFmode register format identical so use define_expand with paradoxical subreg no-op and accompanying new define_split. From-SVN: r8586
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@ -2500,6 +2500,10 @@
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;; The only conversions we will do will be when storing to memory. In that
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;; case, we will use the "frsp" instruction before storing.
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;;
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;; SFmode values are stored in DFmode registers with the same format as
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;; DFmode values, so float_extend is a no-op: treat as paradoxical subreg
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;; using define_expand and define_split if made by combine.
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;;
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;; Note that when we store into a single-precision memory location, we need to
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;; use the frsp insn first. If the register being stored isn't dead, we
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;; need a scratch register for the frsp. But this is difficult when the store
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@ -2507,18 +2511,26 @@
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;; this case, we just lose precision that we would have otherwise gotten but
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;; is not guaranteed. Perhaps this should be tightened up at some point.
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(define_insn "extendsfdf2"
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(define_expand "extendsfdf2"
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[(set (match_operand:DF 0 "gpc_reg_operand" "=f")
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(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
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(match_operand:SF 1 "gpc_reg_operand" "f"))]
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""
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"*
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"
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{
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if (REGNO (operands[0]) == REGNO (operands[1]))
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return \"\";
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else
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return \"fmr %0,%1\";
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}"
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[(set_attr "type" "fp")])
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if (GET_CODE (operands[1]) == SUBREG)
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operands[1] = force_reg (SFmode, operands[1]);
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operands[1] = gen_rtx (SUBREG, DFmode, operands[1], 0);
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}")
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(define_split
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[(set (match_operand:DF 0 "gpc_reg_operand" "")
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(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "")))]
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"GET_CODE (operands[1]) != SUBREG"
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[(set (match_dup 0) (match_dup 1))]
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"
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{
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operands[1] = gen_rtx (SUBREG, DFmode, operands[1], 0);
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}")
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(define_insn "truncdfsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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