invoke.texi (SPARC Options): Document -mfix-ut699.
* doc/invoke.texi (SPARC Options): Document -mfix-ut699. * builtins.c (expand_builtin_mathfn) <BUILT_IN_SQRT>: Try to widen the mode if the instruction isn't available in the original mode. * config/sparc/sparc.opt (mfix-ut699): New option. * config/sparc/sparc.md (muldf3_extend): Disable if -mfix-ut699. (divdf3): Turn into expander. (divdf3_nofix): New insn. (divdf3_fix): Likewise. (divsf3): Disable if -mfix-ut699. (sqrtdf2): Turn into expander. (sqrtdf2_nofix): New insn. (sqrtdf2_fix): Likewise. (sqrtsf2): Disable if -mfix-ut699. From-SVN: r199366
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Eric Botcazou
Eric Botcazou
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2013-05-28 Eric Botcazou <ebotcazou@adacore.com>
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* doc/invoke.texi (SPARC Options): Document -mfix-ut699.
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* builtins.c (expand_builtin_mathfn) <BUILT_IN_SQRT>: Try to widen the
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mode if the instruction isn't available in the original mode.
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* config/sparc/sparc.opt (mfix-ut699): New option.
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* config/sparc/sparc.md (muldf3_extend): Disable if -mfix-ut699.
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(divdf3): Turn into expander.
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(divdf3_nofix): New insn.
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(divdf3_fix): Likewise.
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(divsf3): Disable if -mfix-ut699.
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(sqrtdf2): Turn into expander.
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(sqrtdf2_nofix): New insn.
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(sqrtdf2_fix): Likewise.
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(sqrtsf2): Disable if -mfix-ut699.
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2013-05-27 Richard Biener <rguenther@suse.de>
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PR middle-end/57412
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@ -1961,6 +1961,7 @@ expand_builtin_mathfn (tree exp, rtx target, rtx subtarget)
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tree fndecl = get_callee_fndecl (exp);
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enum machine_mode mode;
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bool errno_set = false;
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bool try_widening = false;
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tree arg;
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if (!validate_arglist (exp, REAL_TYPE, VOID_TYPE))
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@ -1972,6 +1973,7 @@ expand_builtin_mathfn (tree exp, rtx target, rtx subtarget)
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{
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CASE_FLT_FN (BUILT_IN_SQRT):
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errno_set = ! tree_expr_nonnegative_p (arg);
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try_widening = true;
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builtin_optab = sqrt_optab;
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break;
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CASE_FLT_FN (BUILT_IN_EXP):
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@ -2028,8 +2030,10 @@ expand_builtin_mathfn (tree exp, rtx target, rtx subtarget)
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if (! flag_errno_math || ! HONOR_NANS (mode))
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errno_set = false;
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/* Before working hard, check whether the instruction is available. */
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if (optab_handler (builtin_optab, mode) != CODE_FOR_nothing
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/* Before working hard, check whether the instruction is available, but try
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to widen the mode for specific operations. */
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if ((optab_handler (builtin_optab, mode) != CODE_FOR_nothing
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|| (try_widening && !excess_precision_type (TREE_TYPE (exp))))
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&& (!errno_set || !optimize_insn_for_size_p ()))
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{
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rtx result = gen_reg_rtx (mode);
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@ -5499,7 +5499,7 @@
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[(set (match_operand:DF 0 "register_operand" "=e")
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(mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f"))
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(float_extend:DF (match_operand:SF 2 "register_operand" "f"))))]
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"(TARGET_V8 || TARGET_V9) && TARGET_FPU"
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"(TARGET_V8 || TARGET_V9) && TARGET_FPU && !sparc_fix_ut699"
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"fsmuld\t%1, %2, %0"
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[(set_attr "type" "fpmul")
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(set_attr "fptype" "double")])
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@ -5528,20 +5528,37 @@
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"fdivq\t%1, %2, %0"
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[(set_attr "type" "fpdivd")])
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(define_insn "divdf3"
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(define_expand "divdf3"
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[(set (match_operand:DF 0 "register_operand" "=e")
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(div:DF (match_operand:DF 1 "register_operand" "e")
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(match_operand:DF 2 "register_operand" "e")))]
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"TARGET_FPU"
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"")
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(define_insn "*divdf3_nofix"
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[(set (match_operand:DF 0 "register_operand" "=e")
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(div:DF (match_operand:DF 1 "register_operand" "e")
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(match_operand:DF 2 "register_operand" "e")))]
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"TARGET_FPU && !sparc_fix_ut699"
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"fdivd\t%1, %2, %0"
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[(set_attr "type" "fpdivd")
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(set_attr "fptype" "double")])
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(define_insn "*divdf3_fix"
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[(set (match_operand:DF 0 "register_operand" "=e")
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(div:DF (match_operand:DF 1 "register_operand" "e")
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(match_operand:DF 2 "register_operand" "e")))]
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"TARGET_FPU && sparc_fix_ut699"
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"fdivd\t%1, %2, %0\n\tstd\t%0, [%%sp-8]"
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[(set_attr "type" "fpdivd")
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(set_attr "fptype" "double")
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(set_attr "length" "2")])
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(define_insn "divsf3"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(div:SF (match_operand:SF 1 "register_operand" "f")
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(match_operand:SF 2 "register_operand" "f")))]
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"TARGET_FPU"
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"TARGET_FPU && !sparc_fix_ut699"
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"fdivs\t%1, %2, %0"
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[(set_attr "type" "fpdivs")])
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@ -5742,18 +5759,33 @@
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"fsqrtq\t%1, %0"
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[(set_attr "type" "fpsqrtd")])
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(define_insn "sqrtdf2"
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(define_expand "sqrtdf2"
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[(set (match_operand:DF 0 "register_operand" "=e")
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(sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
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"TARGET_FPU"
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"")
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(define_insn "*sqrtdf2_nofix"
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[(set (match_operand:DF 0 "register_operand" "=e")
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(sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
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"TARGET_FPU && !sparc_fix_ut699"
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"fsqrtd\t%1, %0"
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[(set_attr "type" "fpsqrtd")
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(set_attr "fptype" "double")])
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(define_insn "*sqrtdf2_fix"
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[(set (match_operand:DF 0 "register_operand" "=e")
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(sqrt:DF (match_operand:DF 1 "register_operand" "e")))]
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"TARGET_FPU && sparc_fix_ut699"
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"fsqrtd\t%1, %0\n\tstd\t%0, [%%sp-8]"
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[(set_attr "type" "fpsqrtd")
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(set_attr "fptype" "double")
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(set_attr "length" "2")])
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(define_insn "sqrtsf2"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
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"TARGET_FPU"
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"TARGET_FPU && !sparc_fix_ut699"
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"fsqrts\t%1, %0"
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[(set_attr "type" "fpsqrts")])
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@ -201,6 +201,10 @@ Target Report RejectNegative Var(sparc_fix_at697f)
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Enable workaround for single erratum of AT697F processor
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(corresponding to erratum #13 of AT697E processor)
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mfix-ut699
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Target Report RejectNegative Var(sparc_fix_ut699)
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Enable workarounds for the FP errata of the UT699 processor
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Mask(LONG_DOUBLE_128)
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;; Use 128-bit long double
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@ -936,7 +936,7 @@ See RS/6000 and PowerPC Options.
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-mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol
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-mcbcond -mno-cbcond @gol
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-mfmaf -mno-fmaf -mpopc -mno-popc @gol
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-mfix-at697f}
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-mfix-at697f -mfix-ut699}
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@emph{SPU Options}
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@gccoptlist{-mwarn-reloc -merror-reloc @gol
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@ -19449,6 +19449,11 @@ later.
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@opindex mfix-at697f
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Enable the documented workaround for the single erratum of the Atmel AT697F
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processor (which corresponds to erratum #13 of the AT697E processor).
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@item -mfix-ut699
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@opindex mfix-ut699
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Enable the documented workarounds for the floating-point errata of the UT699
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processor.
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@end table
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These @samp{-m} options are supported in addition to the above
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