svn ci -m "introduce bank[0,1] registers and fix rte delay slot scheduling"
2007-06-21 Christian Bruel <christian.bruel@st.com> * config/sh/sh-protos.h (sh_loads_bankedreg_p): Declare. * config/sh/sh.c (sh_loads_bankedreg_p): New function. (push_regs): Changed saving order or banked registers. (sh_expand_epilogue): Likewise. * config/sh/sh.h (BANKED_REGISTER_P): New macro. (FIRST_BANKED_REG): Likewise. (LAST_BANKED_REG): Likewise. * config/sh/sh.md (banked) New attribute. (in_delay_slot): Check banked attribute. 2007-06-21 Christian Bruel <christian.bruel@st.com> * gcc.dg/attr-isr.c: Test delay slot content. From-SVN: r125914
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Christian Bruel
Christian Bruel
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86488aa376
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5c7cafa8dc
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@ -1,3 +1,15 @@
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2007-06-21 Christian Bruel <christian.bruel@st.com>
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* config/sh/sh-protos.h (sh_loads_bankedreg_p): Declare.
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* config/sh/sh.c (sh_loads_bankedreg_p): New function.
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(push_regs): Changed saving order or banked registers.
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(sh_expand_epilogue): Likewise.
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* config/sh/sh.h (BANKED_REGISTER_P): New macro.
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(FIRST_BANKED_REG): Likewise.
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(LAST_BANKED_REG): Likewise.
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* config/sh/sh.md (banked) New attribute.
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(in_delay_slot): Check banked attribute.
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2007-06-20 Sebastian Pop <sebpop@gmail.com>
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PR tree-optimization/32075
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@ -168,6 +168,7 @@ extern rtx replace_n_hard_rtx (rtx, rtx *, int , int);
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extern int shmedia_cleanup_truncate (rtx *, void *);
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extern int sh_contains_memref_p (rtx);
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extern int sh_loads_bankedreg_p (rtx);
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extern rtx shmedia_prepare_call_address (rtx fnaddr, int is_sibcall);
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struct secondary_reload_info;
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extern enum reg_class sh_secondary_reload (bool, rtx, enum reg_class,
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@ -5723,13 +5723,13 @@ pop (int rn)
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static void
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push_regs (HARD_REG_SET *mask, int interrupt_handler)
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{
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int i;
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int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
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int skip_fpscr = 0;
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/* Push PR last; this gives better latencies after the prologue, and
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candidates for the return delay slot when there are no general
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registers pushed. */
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for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
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for (; i < FIRST_PSEUDO_REGISTER; i++)
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{
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/* If this is an interrupt handler, and the SZ bit varies,
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and we have to push any floating point register, we need
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@ -5749,6 +5749,13 @@ push_regs (HARD_REG_SET *mask, int interrupt_handler)
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&& TEST_HARD_REG_BIT (*mask, i))
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push (i);
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}
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/* Push banked registers last to improve delay slot opportunities. */
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if (interrupt_handler)
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for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
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if (TEST_HARD_REG_BIT (*mask, i))
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push (i);
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if (TEST_HARD_REG_BIT (*mask, PR_REG))
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push (PR_REG);
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}
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@ -6675,6 +6682,8 @@ sh_expand_epilogue (bool sibcall_p)
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}
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else /* ! TARGET_SH5 */
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{
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int last_reg;
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save_size = 0;
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if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
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{
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@ -6682,7 +6691,21 @@ sh_expand_epilogue (bool sibcall_p)
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emit_insn (gen_blockage ());
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pop (PR_REG);
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}
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for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
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/* Banked registers are poped first to avoid being scheduled in the
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delay slot. RTE switches banks before the ds instruction. */
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if (current_function_interrupt)
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{
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for (i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
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if (TEST_HARD_REG_BIT (live_regs_mask, i))
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pop (LAST_BANKED_REG - i);
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last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
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}
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else
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last_reg = FIRST_PSEUDO_REGISTER;
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for (i = 0; i < last_reg; i++)
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{
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int j = (FIRST_PSEUDO_REGISTER - 1) - i;
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@ -6692,9 +6715,9 @@ sh_expand_epilogue (bool sibcall_p)
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fpscr_deferred = 1;
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else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j))
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pop (j);
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if (j == FIRST_FP_REG && fpscr_deferred)
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pop (FPSCR_REG);
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}
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}
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if (target_flags != save_flags && ! current_function_interrupt)
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@ -10839,6 +10862,20 @@ sh_contains_memref_p (rtx insn)
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return for_each_rtx (&PATTERN (insn), &sh_contains_memref_p_1, NULL);
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}
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/* Return nonzero iff INSN loads a banked register. */
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int
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sh_loads_bankedreg_p (rtx insn)
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{
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if (GET_CODE (PATTERN (insn)) == SET)
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{
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rtx op = SET_DEST (PATTERN(insn));
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if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
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return 1;
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}
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return 0;
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}
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/* FNADDR is the MEM expression from a call expander. Return an address
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to use in an SHmedia insn pattern. */
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rtx
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@ -1033,6 +1033,16 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
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#define FIRST_TARGET_REG TR0_REG
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#define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
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/* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
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#define FIRST_BANKED_REG R0_REG
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#define LAST_BANKED_REG R7_REG
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#define BANKED_REGISTER_P(REGNO) \
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IN_RANGE ((REGNO), \
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(unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
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(unsigned HOST_WIDE_INT) LAST_BANKED_REG)
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#define GENERAL_REGISTER_P(REGNO) \
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IN_RANGE ((REGNO), \
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(unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
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@ -463,6 +463,12 @@
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(define_attr "needs_delay_slot" "yes,no" (const_string "no"))
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(define_attr "banked" "yes,no"
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(cond [(eq (symbol_ref "sh_loads_bankedreg_p (insn)")
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(const_int 1))
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(const_string "yes")]
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(const_string "no")))
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;; ??? This should be (nil) instead of (const_int 0)
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(define_attr "hit_stack" "yes,no"
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(cond [(eq (symbol_ref "find_regno_note (insn, REG_INC, SP_REG)")
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@ -541,8 +547,9 @@
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(eq_attr "type" "!pload,prset"))
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(and (eq_attr "interrupt_function" "yes")
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(ior
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(ne (symbol_ref "TARGET_SH3") (const_int 0))
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(eq_attr "hit_stack" "no"))))) (nil) (nil)])
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(eq (symbol_ref "TARGET_SH3") (const_int 0))
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(eq_attr "hit_stack" "no")
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(eq_attr "banked" "no"))))) (nil) (nil)])
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;; Since a call implicitly uses the PR register, we can't allow
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;; a PR register store in a jsr delay slot.
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@ -1,3 +1,7 @@
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2007-06-21 Christian Bruel <christian.bruel@st.com>
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* gcc.dg/attr-isr.c: Test delay slot content.
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2007-06-20 Jerry DeLisle <jvdelisle@gcc.gnu.org>
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PR fortran/32361
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@ -16,3 +16,4 @@ void
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/* { dg-final { scan-assembler-times "\[^f\]r\[0-9\]\[ \t\]*," 8 } } */
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/* { dg-final { scan-assembler-not "\[^f\]r1\[0-3\]" } } */
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/* { dg-final { scan-assembler-times "macl" 2} } */
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/* { dg-final { scan-assembler-not "rte.*\n.*r15\[+\],r\[0-7\]\n" } } */
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