i386: Add define_insn_and_split patterns for btrl [PR96938]
In the following testcase we only optimize f2 and f7 to btrl, although we should optimize that way all of the functions. The problem is the type demotion/narrowing (which is performed solely during the generic folding and not later), without it we see the AND performed in SImode and match it as btrl, but with it while the shifts are still performed in SImode, the AND is already done in QImode or HImode low part of the shift. 2021-01-13 Jakub Jelinek <jakub@redhat.com> PR target/96938 * config/i386/i386.md (*btr<mode>_1, *btr<mode>_2): New define_insn_and_split patterns. (splitter after *btr<mode>_2): New splitter. * gcc.target/i386/pr96938.c: New test.
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@ -12419,6 +12419,71 @@
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(match_dup 3)))
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(clobber (reg:CC FLAGS_REG))])])
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(define_insn_and_split "*btr<mode>_1"
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[(set (match_operand:SWI12 0 "register_operand")
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(and:SWI12
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(subreg:SWI12
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(rotate:SI (const_int -2)
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(match_operand:QI 2 "register_operand")) 0)
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(match_operand:SWI12 1 "nonimmediate_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_USE_BT && ix86_pre_reload_split ()"
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"#"
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"&& 1"
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[(parallel
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[(set (match_dup 0)
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(and:SI (rotate:SI (const_int -2) (match_dup 2))
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(match_dup 1)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[0] = lowpart_subreg (SImode, operands[0], <MODE>mode);
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if (MEM_P (operands[1]))
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operands[1] = force_reg (<MODE>mode, operands[1]);
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operands[1] = lowpart_subreg (SImode, operands[1], <MODE>mode);
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})
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(define_insn_and_split "*btr<mode>_2"
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[(set (zero_extract:HI
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(match_operand:SWI12 0 "nonimmediate_operand")
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(const_int 1)
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(zero_extend:SI (match_operand:QI 1 "register_operand")))
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(const_int 0))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_USE_BT && ix86_pre_reload_split ()"
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"#"
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"&& MEM_P (operands[0])"
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[(set (match_dup 2) (match_dup 0))
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(parallel
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[(set (match_dup 3)
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(and:SI (rotate:SI (const_int -2) (match_dup 1))
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(match_dup 4)))
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(clobber (reg:CC FLAGS_REG))])
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(set (match_dup 0) (match_dup 5))]
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{
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operands[2] = gen_reg_rtx (<MODE>mode);
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operands[5] = gen_reg_rtx (<MODE>mode);
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operands[3] = lowpart_subreg (SImode, operands[5], <MODE>mode);
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operands[4] = lowpart_subreg (SImode, operands[2], <MODE>mode);
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})
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(define_split
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[(set (zero_extract:HI
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(match_operand:SWI12 0 "register_operand")
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(const_int 1)
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(zero_extend:SI (match_operand:QI 1 "register_operand")))
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(const_int 0))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_USE_BT && ix86_pre_reload_split ()"
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[(parallel
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[(set (match_dup 0)
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(and:SI (rotate:SI (const_int -2) (match_dup 1))
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(match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[2] = lowpart_subreg (SImode, operands[0], <MODE>mode);
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operands[0] = lowpart_subreg (SImode, operands[0], <MODE>mode);
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})
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;; These instructions are never faster than the corresponding
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;; and/ior/xor operations when using immediate operand, so with
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;; 32-bit there's no point. But in 64-bit, we can't hold the
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@ -0,0 +1,66 @@
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/* PR target/96938 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -masm=att" } */
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/* { dg-final { scan-assembler-times "\tbtrl\t" 10 } } */
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void
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f1 (unsigned char *f, int o, unsigned char v)
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{
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*f = (*f & ~(1 << o)) | (v << o);
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}
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void
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f2 (unsigned char *f, int o, unsigned char v)
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{
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int t = *f & ~(1 << o);
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*f = t | (v << o);
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}
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void
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f3 (unsigned char *f, int o, unsigned char v)
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{
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*f &= ~(1 << o);
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}
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void
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f4 (unsigned char *f, int o, unsigned char v)
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{
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*f = (*f & ~(1 << (o & 31))) | v;
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}
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void
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f5 (unsigned char *f, int o, unsigned char v)
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{
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*f = (*f & ~(1 << (o & 31))) | (v << (o & 31));
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}
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void
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f6 (unsigned short *f, int o, unsigned short v)
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{
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*f = (*f & ~(1 << o)) | (v << o);
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}
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void
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f7 (unsigned short *f, int o, unsigned short v)
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{
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int t = *f & ~(1 << o);
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*f = t | (v << o);
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}
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void
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f8 (unsigned short *f, int o, unsigned short v)
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{
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*f &= ~(1 << o);
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}
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void
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f9 (unsigned short *f, int o, unsigned short v)
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{
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*f = (*f & ~(1 << (o & 31))) | v;
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}
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void
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f10 (unsigned short *f, int o, unsigned short v)
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{
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*f = (*f & ~(1 << (o & 31))) | (v << (o & 31));
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}
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