re PR target/51244 ([SH] Inefficient conditional branch and code around T bit)
PR target/51244 * config/sh/sh_treg_combine.cc: New SH specific RTL pass. * config.gcc (SH extra_objs): Add sh_ifcvt.o. * config/sh/t-sh (sh_treg_combine.o): New entry. * config/sh/sh.c (sh_fixed_condition_code_regs): New function that implements the target hook TARGET_FIXED_CONDITION_CODE_REGS. (register_sh_passes): New function. Register sh_treg_combine pass. (sh_option_override): Invoke it. (sh_canonicalize_comparison): Handle op0_preserve_value. * sh.md (*cbranch_t"): Do not try to optimize missed test and branch opportunities. Canonicalize branch condition. (nott): Allow only if pseudos can be created for non-SH2A. PR target/51244 * gcc.dg/torture/p51244-21.c: New. * gcc.target/sh/pr51244-20.c: New. * gcc.target/sh/pr51244-20-sh2a.c: New. From-SVN: r203492
This commit is contained in:
Oleg Endo
parent
585a0b9916
commit
5d30dc5b6d
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@ -1,3 +1,18 @@
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2013-10-12 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/51244
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* config/sh/sh_treg_combine.cc: New SH specific RTL pass.
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* config.gcc (SH extra_objs): Add sh_ifcvt.o.
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* config/sh/t-sh (sh_treg_combine.o): New entry.
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* config/sh/sh.c (sh_fixed_condition_code_regs): New function that
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implements the target hook TARGET_FIXED_CONDITION_CODE_REGS.
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(register_sh_passes): New function. Register sh_treg_combine pass.
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(sh_option_override): Invoke it.
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(sh_canonicalize_comparison): Handle op0_preserve_value.
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* sh.md (*cbranch_t"): Do not try to optimize missed test and branch
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opportunities. Canonicalize branch condition.
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(nott): Allow only if pseudos can be created for non-SH2A.
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2013-10-12 H.J. Lu <hongjiu.lu@intel.com>
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PR target/58690
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@ -465,6 +465,7 @@ sh[123456789lbe]*-*-* | sh-*-*)
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cpu_type=sh
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need_64bit_hwint=yes
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extra_options="${extra_options} fused-madd.opt"
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extra_objs="${extra_objs} sh_treg_combine.o"
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;;
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v850*-*-*)
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cpu_type=v850
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@ -53,6 +53,9 @@ along with GCC; see the file COPYING3. If not see
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#include "alloc-pool.h"
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#include "tm-constrs.h"
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#include "opts.h"
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#include "tree-pass.h"
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#include "pass_manager.h"
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#include "context.h"
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#include <sstream>
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#include <vector>
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@ -311,6 +314,7 @@ static bool sequence_insn_p (rtx);
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static void sh_canonicalize_comparison (int *, rtx *, rtx *, bool);
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static void sh_canonicalize_comparison (enum rtx_code&, rtx&, rtx&,
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enum machine_mode, bool);
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static bool sh_fixed_condition_code_regs (unsigned int* p1, unsigned int* p2);
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static void sh_init_sync_libfuncs (void) ATTRIBUTE_UNUSED;
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@ -587,6 +591,9 @@ static const struct attribute_spec sh_attribute_table[] =
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#undef TARGET_CANONICALIZE_COMPARISON
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#define TARGET_CANONICALIZE_COMPARISON sh_canonicalize_comparison
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#undef TARGET_FIXED_CONDITION_CODE_REGS
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#define TARGET_FIXED_CONDITION_CODE_REGS sh_fixed_condition_code_regs
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/* Machine-specific symbol_ref flags. */
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#define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
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@ -710,6 +717,34 @@ got_mode_name:;
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#undef err_ret
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}
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/* Register SH specific RTL passes. */
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extern opt_pass* make_pass_sh_treg_combine (gcc::context* ctx, bool split_insns,
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const char* name);
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static void
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register_sh_passes (void)
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{
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if (!TARGET_SH1)
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return;
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/* Running the sh_treg_combine pass after ce1 generates better code when
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comparisons are combined and reg-reg moves are introduced, because
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reg-reg moves will be eliminated afterwards. However, there are quite
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some cases where combine will be unable to fold comparison related insns,
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thus for now don't do it.
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register_pass (make_pass_sh_treg_combine (g, false, "sh_treg_combine1"),
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PASS_POS_INSERT_AFTER, "ce1", 1);
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*/
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/* Run sh_treg_combine pass after combine but before register allocation. */
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register_pass (make_pass_sh_treg_combine (g, true, "sh_treg_combine2"),
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PASS_POS_INSERT_AFTER, "split1", 1);
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/* Run sh_treg_combine pass after register allocation and basic block
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reordering as this sometimes creates new opportunities. */
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register_pass (make_pass_sh_treg_combine (g, true, "sh_treg_combine3"),
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PASS_POS_INSERT_AFTER, "split4", 1);
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}
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/* Implement TARGET_OPTION_OVERRIDE macro. Validate and override
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various options, and do some machine dependent initialization. */
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static void
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@ -1022,6 +1057,8 @@ sh_option_override (void)
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target CPU. */
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selected_atomic_model_
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= parse_validate_atomic_model_option (sh_atomic_model_str);
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register_sh_passes ();
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}
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/* Print the operand address in x to the stream. */
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@ -1908,7 +1945,7 @@ prepare_move_operands (rtx operands[], enum machine_mode mode)
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static void
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sh_canonicalize_comparison (enum rtx_code& cmp, rtx& op0, rtx& op1,
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enum machine_mode mode,
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bool op0_preserve_value ATTRIBUTE_UNUSED)
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bool op0_preserve_value)
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{
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/* When invoked from within the combine pass the mode is not specified,
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so try to get it from one of the operands. */
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@ -1928,6 +1965,9 @@ sh_canonicalize_comparison (enum rtx_code& cmp, rtx& op0, rtx& op1,
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// Make sure that the constant operand is the second operand.
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if (CONST_INT_P (op0) && !CONST_INT_P (op1))
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{
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if (op0_preserve_value)
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return;
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std::swap (op0, op1);
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cmp = swap_condition (cmp);
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}
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@ -2016,6 +2056,14 @@ sh_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
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*code = (int)tmp_code;
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}
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bool
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sh_fixed_condition_code_regs (unsigned int* p1, unsigned int* p2)
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{
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*p1 = T_REG;
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*p2 = INVALID_REGNUM;
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return true;
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}
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enum rtx_code
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prepare_cbranch_operands (rtx *operands, enum machine_mode mode,
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enum rtx_code comparison)
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@ -8419,89 +8419,32 @@ label:
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return output_branch (sh_eval_treg_value (operands[1]), insn, operands);
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}
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"&& 1"
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[(set (pc) (if_then_else (eq (reg:SI T_REG) (match_dup 2))
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(label_ref (match_dup 0))
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(pc)))]
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[(const_int 0)]
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{
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/* Try to find missed test and branch combine opportunities which result
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in redundant T bit tests before conditional branches.
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This is done not only after combine (and before reload) but in every
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split pass, because some opportunities are formed also after combine.
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FIXME: Probably this would not be needed if CCmode was used
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together with TARGET_FIXED_CONDITION_CODE_REGS. */
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/* Try to canonicalize the branch condition if it is not one of:
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(ne (reg:SI T_REG) (const_int 0))
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(eq (reg:SI T_REG) (const_int 0))
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const int treg_value = sh_eval_treg_value (operands[1]);
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operands[2] = NULL_RTX;
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Instead of splitting out a new insn, we modify the current insn's
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operands as needed. This preserves things such as REG_DEAD notes. */
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/* Scan the insns backwards for an insn that sets the T bit by testing a
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reg against zero like:
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(set (reg T_REG) (eq (reg) (const_int 0))) */
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rtx testing_insn = NULL_RTX;
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rtx tested_reg = NULL_RTX;
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if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
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&& REG_P (XEXP (operands[1], 0)) && REGNO (XEXP (operands[1], 0)) == T_REG
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&& XEXP (operands[1], 1) == const0_rtx)
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DONE;
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set_of_reg s0 = sh_find_set_of_reg (get_t_reg_rtx (), curr_insn,
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prev_nonnote_insn_bb);
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if (s0.set_src != NULL_RTX
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&& GET_CODE (s0.set_src) == EQ
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&& REG_P (XEXP (s0.set_src, 0))
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&& satisfies_constraint_Z (XEXP (s0.set_src, 1)))
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{
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testing_insn = s0.insn;
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tested_reg = XEXP (s0.set_src, 0);
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}
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else
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FAIL;
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int branch_cond = sh_eval_treg_value (operands[1]);
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rtx new_cond_rtx = NULL_RTX;
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/* Continue scanning the insns backwards and try to find the insn that
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sets the tested reg which we found above. If the reg is set by storing
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the T bit or the negated T bit we can eliminate the test insn before
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the branch. Notice that the branch condition has to be inverted if the
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test is eliminated. */
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if (branch_cond == 0)
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new_cond_rtx = gen_rtx_EQ (VOIDmode, get_t_reg_rtx (), const0_rtx);
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else if (branch_cond == 1)
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new_cond_rtx = gen_rtx_NE (VOIDmode, get_t_reg_rtx (), const0_rtx);
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/* If the T bit is used between the testing insn and the brach insn
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leave it alone. */
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if (reg_used_between_p (get_t_reg_rtx (), testing_insn, curr_insn))
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FAIL;
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while (true)
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{
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/* It's not safe to go beyond the current basic block after reload. */
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set_of_reg s1 = sh_find_set_of_reg (tested_reg, s0.insn,
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reload_completed
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? prev_nonnote_insn_bb
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: prev_nonnote_insn);
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if (s1.set_src == NULL_RTX)
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break;
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if (t_reg_operand (s1.set_src, VOIDmode))
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operands[2] = GEN_INT (treg_value ^ 1);
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else if (negt_reg_operand (s1.set_src, VOIDmode))
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operands[2] = GEN_INT (treg_value);
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else if (REG_P (s1.set_src))
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{
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/* If it's a reg-reg copy follow the copied reg. This can
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happen e.g. when T bit store zero-extensions are
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eliminated. */
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tested_reg = s1.set_src;
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s0.insn = s1.insn;
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continue;
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}
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/* It's only safe to remove the testing insn if the T bit is not
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modified between the testing insn and the insn that stores the
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T bit. Notice that some T bit stores such as negc also modify
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the T bit. */
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if (modified_between_p (get_t_reg_rtx (), s1.insn, testing_insn)
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|| modified_in_p (get_t_reg_rtx (), s1.insn))
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operands[2] = NULL_RTX;
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break;
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}
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if (operands[2] == NULL_RTX)
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FAIL;
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set_insn_deleted (testing_insn);
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if (new_cond_rtx != NULL_RTX)
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validate_change (curr_insn, &XEXP (XEXP (PATTERN (curr_insn), 1), 0),
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new_cond_rtx, false);
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DONE;
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}
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[(set_attr "type" "cbranch")])
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@ -11480,10 +11423,13 @@ label:
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;; multiple insns like:
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;; movt Rn
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;; tst Rn,Rn
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;; This requires an additional pseudo. The SH specific sh_treg_combine RTL
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;; pass will look for this insn. Disallow using it if pseudos can't be
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;; created.
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(define_insn_and_split "nott"
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[(set (reg:SI T_REG)
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(xor:SI (match_operand:SI 0 "t_reg_operand" "") (const_int 1)))]
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"TARGET_SH1"
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(xor:SI (match_operand:SI 0 "t_reg_operand") (const_int 1)))]
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"TARGET_SH2A || (TARGET_SH1 && can_create_pseudo_p ())"
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{
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gcc_assert (TARGET_SH2A);
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return "nott";
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File diff suppressed because it is too large
Load Diff
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@ -21,6 +21,10 @@ sh-c.o: $(srcdir)/config/sh/sh-c.c \
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$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) \
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$(srcdir)/config/sh/sh-c.c
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sh_treg_combine.o: $(srcdir)/config/sh/sh_treg_combine.cc \
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$(CONFIG_H) $(SYSTEM_H) $(TREE_H) $(TM_H) $(TM_P_H) coretypes.h
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$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
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DEFAULT_ENDIAN = $(word 1,$(TM_ENDIAN_CONFIG))
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OTHER_ENDIAN = $(word 2,$(TM_ENDIAN_CONFIG))
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@ -1,3 +1,10 @@
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2013-10-12 Oleg Endo <olegendo@gcc.gnu.org>
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PR target/51244
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* gcc.dg/torture/p51244-21.c: New.
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* gcc.target/sh/pr51244-20.c: New.
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* gcc.target/sh/pr51244-20-sh2a.c: New.
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2013-10-12 Arnaud Charlet <charlet@adacore.com>
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* gnat.dg/specs/linker_section.ads: Update test.
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@ -0,0 +1,75 @@
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/* { dg-do run } */
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#include <assert.h>
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static inline int
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blk_oversized_queue (int* q)
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{
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if (q[2])
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return q[1] != 0;
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return q[0] == 0;
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}
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int __attribute__ ((noinline))
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get_request (int* q, int rw)
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{
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if (blk_oversized_queue (q))
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{
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if ((rw == 1) || (rw == 0))
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return -33;
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return 0;
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}
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return -100;
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}
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int main (void)
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{
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int x[3];
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int r;
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x[0] = 0; x[1] = 1; x[2] = 1;
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r = get_request (x, 0);
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assert (r == -33);
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r = get_request (x, 1);
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assert (r == -33);
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r = get_request (x, 2);
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assert (r == 0);
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x[0] = 0; x[1] = 0; x[2] = 1;
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r = get_request (x, 0);
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assert (r == -100);
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r = get_request (x, 1);
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assert (r == -100);
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r = get_request (x, 2);
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assert (r == -100);
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x[0] = 0; x[1] = 0; x[2] = 0;
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r = get_request (x, 0);
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assert (r == -33);
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r = get_request (x, 1);
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assert (r == -33);
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r = get_request (x, 2);
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assert (r == 0);
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x[0] = 0; x[1] = 0; x[2] = 0;
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r = get_request (x, 0);
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assert (r == -33);
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r = get_request (x, 1);
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assert (r == -33);
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r = get_request (x, 2);
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assert (r == 0);
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return 0;
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}
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@ -0,0 +1,14 @@
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/* Check that the SH specific sh_treg_combine RTL optimization pass works as
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expected. */
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/* { dg-do compile { target "sh*-*-*" } } */
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/* { dg-options "-O2" } */
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/* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */
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/* { dg-final { scan-assembler-times "tst" 5 } } */
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/* { dg-final { scan-assembler-times "movt" 0 } } */
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/* { dg-final { scan-assembler-times "nott" 1 } } */
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/* { dg-final { scan-assembler-times "cmp/eq" 2 } } */
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/* { dg-final { scan-assembler-times "cmp/hi" 4 } } */
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/* { dg-final { scan-assembler-times "cmp/gt" 3 } } */
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/* { dg-final { scan-assembler-times "not\t" 1 } } */
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#include "pr51244-20.c"
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@ -0,0 +1,103 @@
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/* Check that the SH specific sh_treg_combine RTL optimization pass works as
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expected. On SH2A the expected insns are slightly different, see
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pr51244-21.c. */
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/* { dg-do compile { target "sh*-*-*" } } */
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/* { dg-options "-O2" } */
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/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */
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/* { dg-final { scan-assembler-times "tst" 6 } } */
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/* { dg-final { scan-assembler-times "movt" 1 } } */
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/* { dg-final { scan-assembler-times "cmp/eq" 2 } } */
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/* { dg-final { scan-assembler-times "cmp/hi" 4 } } */
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/* { dg-final { scan-assembler-times "cmp/gt" 2 } } */
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/* { dg-final { scan-assembler-times "not\t" 1 } } */
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/* non-SH2A: 2x tst, 1x movt, 2x cmp/eq, 1x cmp/hi
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SH2A: 1x tst, 1x nott, 2x cmp/eq, 1x cmp/hi */
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static inline int
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blk_oversized_queue_0 (int* q)
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{
|
||||
if (q[2])
|
||||
return q[1] == 5;
|
||||
return (q[0] != 5);
|
||||
}
|
||||
|
||||
int __attribute__ ((noinline))
|
||||
get_request_0 (int* q, int rw)
|
||||
{
|
||||
if (blk_oversized_queue_0 (q))
|
||||
{
|
||||
if ((rw == 1) || (rw == 0))
|
||||
return -33;
|
||||
return 0;
|
||||
}
|
||||
return -100;
|
||||
}
|
||||
|
||||
|
||||
/* 1x tst, 1x cmp/gt, 1x cmp/hi
|
||||
On SH2A mem loads/stores have a wrong length of 4 bytes and thus will
|
||||
not be placed in a delay slot. This introduces an extra cmp/gt insn. */
|
||||
static inline int
|
||||
blk_oversized_queue_1 (int* q)
|
||||
{
|
||||
if (q[2])
|
||||
return q[1] > 5;
|
||||
return (q[0] > 5);
|
||||
}
|
||||
|
||||
int __attribute__ ((noinline))
|
||||
get_request_1 (int* q, int rw)
|
||||
{
|
||||
if (blk_oversized_queue_1 (q))
|
||||
{
|
||||
if ((rw == 1) || (rw == 0))
|
||||
return -33;
|
||||
return 0;
|
||||
}
|
||||
return -100;
|
||||
}
|
||||
|
||||
|
||||
/* 1x tst, 1x cmp/gt, 1x cmp/hi, 1x cmp/hi */
|
||||
static inline int
|
||||
blk_oversized_queue_2 (int* q)
|
||||
{
|
||||
if (q[2])
|
||||
return q[1] > 5;
|
||||
return (q[0] < 5);
|
||||
}
|
||||
|
||||
int __attribute__ ((noinline))
|
||||
get_request_2 (int* q, int rw)
|
||||
{
|
||||
if (blk_oversized_queue_2 (q))
|
||||
{
|
||||
if ((rw == 1) || (rw == 0))
|
||||
return -33;
|
||||
return 0;
|
||||
}
|
||||
return -100;
|
||||
}
|
||||
|
||||
|
||||
/* 2x tst, 1x cmp/hi, 1x not */
|
||||
static inline int
|
||||
blk_oversized_queue_5 (int* q)
|
||||
{
|
||||
if (q[2])
|
||||
return q[1] != 0;
|
||||
return q[0] == 0;
|
||||
}
|
||||
|
||||
int __attribute__ ((noinline))
|
||||
get_request_5 (int* q, int rw)
|
||||
{
|
||||
if (blk_oversized_queue_5 (q))
|
||||
{
|
||||
if ((rw == 1) || (rw == 0))
|
||||
return -33;
|
||||
return 0;
|
||||
}
|
||||
return -100;
|
||||
}
|
||||
Loading…
Reference in New Issue