Add execution + assembler tests of the AArch64 ZIP Intrinsics.
* gcc.target/aarch64/simd/simd.exp: New file. * gcc.target/aarch64/simd/vzipf32_1.c: New file. * gcc.target/aarch64/simd/vzipf32.x: New file. * gcc.target/aarch64/simd/vzipp16_1.c: New file. * gcc.target/aarch64/simd/vzipp16.x: New file. * gcc.target/aarch64/simd/vzipp8_1.c: New file. * gcc.target/aarch64/simd/vzipp8.x: New file. * gcc.target/aarch64/simd/vzipqf32_1.c: New file. * gcc.target/aarch64/simd/vzipqf32.x: New file. * gcc.target/aarch64/simd/vzipqp16_1.c: New file. * gcc.target/aarch64/simd/vzipqp16.x: New file. * gcc.target/aarch64/simd/vzipqp8_1.c: New file. * gcc.target/aarch64/simd/vzipqp8.x: New file. * gcc.target/aarch64/simd/vzipqs16_1.c: New file. * gcc.target/aarch64/simd/vzipqs16.x: New file. * gcc.target/aarch64/simd/vzipqs32_1.c: New file. * gcc.target/aarch64/simd/vzipqs32.x: New file. * gcc.target/aarch64/simd/vzipqs8_1.c: New file. * gcc.target/aarch64/simd/vzipqs8.x: New file. * gcc.target/aarch64/simd/vzipqu16_1.c: New file. * gcc.target/aarch64/simd/vzipqu16.x: New file. * gcc.target/aarch64/simd/vzipqu32_1.c: New file. * gcc.target/aarch64/simd/vzipqu32.x: New file. * gcc.target/aarch64/simd/vzipqu8_1.c: New file. * gcc.target/aarch64/simd/vzipqu8.x: New file. * gcc.target/aarch64/simd/vzips16_1.c: New file. * gcc.target/aarch64/simd/vzips16.x: New file. * gcc.target/aarch64/simd/vzips32_1.c: New file. * gcc.target/aarch64/simd/vzips32.x: New file. * gcc.target/aarch64/simd/vzips8_1.c: New file. * gcc.target/aarch64/simd/vzips8.x: New file. * gcc.target/aarch64/simd/vzipu16_1.c: New file. * gcc.target/aarch64/simd/vzipu16.x: New file. * gcc.target/aarch64/simd/vzipu32_1.c: New file. * gcc.target/aarch64/simd/vzipu32.x: New file. * gcc.target/aarch64/simd/vzipu8_1.c: New file. * gcc.target/aarch64/simd/vzipu8.x: New file. From-SVN: r209893
This commit is contained in:
Alan Lawrence
Alan Lawrence
parent
e3f613cbbc
commit
5d3ad081b1
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@ -1,3 +1,43 @@
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2014-04-29 Alan Lawrence <alan.lawrence@arm.com>
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* gcc.target/aarch64/simd/simd.exp: New file.
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* gcc.target/aarch64/simd/vzipf32_1.c: New file.
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* gcc.target/aarch64/simd/vzipf32.x: New file.
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* gcc.target/aarch64/simd/vzipp16_1.c: New file.
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* gcc.target/aarch64/simd/vzipp16.x: New file.
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* gcc.target/aarch64/simd/vzipp8_1.c: New file.
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* gcc.target/aarch64/simd/vzipp8.x: New file.
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* gcc.target/aarch64/simd/vzipqf32_1.c: New file.
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* gcc.target/aarch64/simd/vzipqf32.x: New file.
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* gcc.target/aarch64/simd/vzipqp16_1.c: New file.
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* gcc.target/aarch64/simd/vzipqp16.x: New file.
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* gcc.target/aarch64/simd/vzipqp8_1.c: New file.
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* gcc.target/aarch64/simd/vzipqp8.x: New file.
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* gcc.target/aarch64/simd/vzipqs16_1.c: New file.
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* gcc.target/aarch64/simd/vzipqs16.x: New file.
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* gcc.target/aarch64/simd/vzipqs32_1.c: New file.
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* gcc.target/aarch64/simd/vzipqs32.x: New file.
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* gcc.target/aarch64/simd/vzipqs8_1.c: New file.
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* gcc.target/aarch64/simd/vzipqs8.x: New file.
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* gcc.target/aarch64/simd/vzipqu16_1.c: New file.
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* gcc.target/aarch64/simd/vzipqu16.x: New file.
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* gcc.target/aarch64/simd/vzipqu32_1.c: New file.
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* gcc.target/aarch64/simd/vzipqu32.x: New file.
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* gcc.target/aarch64/simd/vzipqu8_1.c: New file.
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* gcc.target/aarch64/simd/vzipqu8.x: New file.
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* gcc.target/aarch64/simd/vzips16_1.c: New file.
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* gcc.target/aarch64/simd/vzips16.x: New file.
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* gcc.target/aarch64/simd/vzips32_1.c: New file.
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* gcc.target/aarch64/simd/vzips32.x: New file.
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* gcc.target/aarch64/simd/vzips8_1.c: New file.
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* gcc.target/aarch64/simd/vzips8.x: New file.
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* gcc.target/aarch64/simd/vzipu16_1.c: New file.
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* gcc.target/aarch64/simd/vzipu16.x: New file.
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* gcc.target/aarch64/simd/vzipu32_1.c: New file.
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* gcc.target/aarch64/simd/vzipu32.x: New file.
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* gcc.target/aarch64/simd/vzipu8_1.c: New file.
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* gcc.target/aarch64/simd/vzipu8.x: New file.
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2014-04-29 Zhenqiang Chen <zhenqiang.chen@linaro.org>
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* gcc.target/aarch64/fcsel_1.c: New test case.
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@ -0,0 +1,45 @@
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# Specific regression driver for AArch64 SIMD instructions.
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# Copyright (C) 2014 Free Software Foundation, Inc.
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# Contributed by ARM Ltd.
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#
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# This file is part of GCC.
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#
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# GCC is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3, or (at your option)
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# any later version.
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#
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# GCC is distributed in the hope that it will be useful, but
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# WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with GCC; see the file COPYING3. If not see
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# <http://www.gnu.org/licenses/>. */
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# GCC testsuite that uses the `dg.exp' driver.
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# Exit immediately if this isn't an AArch64 target.
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if {![istarget aarch64*-*-*] } then {
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return
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}
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# Load support procs.
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load_lib gcc-dg.exp
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# If a testcase doesn't have special options, use these.
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global DEFAULT_CFLAGS
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if ![info exists DEFAULT_CFLAGS] then {
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set DEFAULT_CFLAGS " -ansi -pedantic-errors"
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}
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# Initialize `dg'.
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dg-init
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# Main loop.
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dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
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"" $DEFAULT_CFLAGS
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# All done.
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dg-finish
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@ -0,0 +1,27 @@
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extern void abort (void);
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float32x2x2_t
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test_vzipf32 (float32x2_t _a, float32x2_t _b)
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{
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return vzip_f32 (_a, _b);
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}
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int
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main (int argc, char **argv)
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{
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int i;
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float32_t first[] = {1, 2};
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float32_t second[] = {3, 4};
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float32x2x2_t result = test_vzipf32 (vld1_f32 (first), vld1_f32 (second));
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float32x2_t res1 = result.val[0], res2 = result.val[1];
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float32_t exp1[] = {1, 3};
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float32_t exp2[] = {2, 4};
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float32x2_t expected1 = vld1_f32 (exp1);
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float32x2_t expected2 = vld1_f32 (exp2);
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for (i = 0; i < 2; i++)
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if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
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abort ();
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return 0;
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}
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/* Test the `vzip_f32' AArch64 SIMD intrinsic. */
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/* { dg-do run } */
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/* { dg-options "-save-temps -fno-inline" } */
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#include <arm_neon.h>
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#include "vzipf32.x"
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/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
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/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
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/* { dg-final { cleanup-saved-temps } } */
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extern void abort (void);
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poly16x4x2_t
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test_vzipp16 (poly16x4_t _a, poly16x4_t _b)
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{
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return vzip_p16 (_a, _b);
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}
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int
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main (int argc, char **argv)
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{
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int i;
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poly16_t first[] = {1, 2, 3, 4};
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poly16_t second[] = {5, 6, 7, 8};
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poly16x4x2_t result = test_vzipp16 (vld1_p16 (first), vld1_p16 (second));
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poly16x4_t res1 = result.val[0], res2 = result.val[1];
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poly16_t exp1[] = {1, 5, 2, 6};
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poly16_t exp2[] = {3, 7, 4, 8};
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poly16x4_t expected1 = vld1_p16 (exp1);
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poly16x4_t expected2 = vld1_p16 (exp2);
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for (i = 0; i < 4; i++)
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if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
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abort ();
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return 0;
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}
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/* Test the `vzip_p16' AArch64 SIMD intrinsic. */
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/* { dg-do run } */
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/* { dg-options "-save-temps -fno-inline" } */
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#include <arm_neon.h>
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#include "vzipp16.x"
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/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
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/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
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/* { dg-final { cleanup-saved-temps } } */
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extern void abort (void);
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poly8x8x2_t
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test_vzipp8 (poly8x8_t _a, poly8x8_t _b)
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{
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return vzip_p8 (_a, _b);
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}
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int
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main (int argc, char **argv)
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{
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int i;
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poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
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poly8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
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poly8x8x2_t result = test_vzipp8 (vld1_p8 (first), vld1_p8 (second));
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poly8x8_t res1 = result.val[0], res2 = result.val[1];
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poly8_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
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poly8_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
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poly8x8_t expected1 = vld1_p8 (exp1);
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poly8x8_t expected2 = vld1_p8 (exp2);
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for (i = 0; i < 8; i++)
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if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
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abort ();
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return 0;
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}
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/* Test the `vzip_p8' AArch64 SIMD intrinsic. */
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/* { dg-do run } */
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/* { dg-options "-save-temps -fno-inline" } */
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#include <arm_neon.h>
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#include "vzipp8.x"
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/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
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/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
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/* { dg-final { cleanup-saved-temps } } */
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extern void abort (void);
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float32x4x2_t
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test_vzipqf32 (float32x4_t _a, float32x4_t _b)
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{
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return vzipq_f32 (_a, _b);
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}
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int
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main (int argc, char **argv)
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{
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int i;
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float32_t first[] = {1, 2, 3, 4};
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float32_t second[] = {5, 6, 7, 8};
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float32x4x2_t result = test_vzipqf32 (vld1q_f32 (first), vld1q_f32 (second));
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float32x4_t res1 = result.val[0], res2 = result.val[1];
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float32_t exp1[] = {1, 5, 2, 6};
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float32_t exp2[] = {3, 7, 4, 8};
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float32x4_t expected1 = vld1q_f32 (exp1);
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float32x4_t expected2 = vld1q_f32 (exp2);
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for (i = 0; i < 4; i++)
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if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
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abort ();
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return 0;
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}
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/* Test the `vzipq_f32' AArch64 SIMD intrinsic. */
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/* { dg-do run } */
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/* { dg-options "-save-temps -fno-inline" } */
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#include <arm_neon.h>
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#include "vzipqf32.x"
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/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
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/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
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/* { dg-final { cleanup-saved-temps } } */
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extern void abort (void);
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poly16x8x2_t
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test_vzipqp16 (poly16x8_t _a, poly16x8_t _b)
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{
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return vzipq_p16 (_a, _b);
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}
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int
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main (int argc, char **argv)
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{
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int i;
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poly16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
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poly16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
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poly16x8x2_t result = test_vzipqp16 (vld1q_p16 (first), vld1q_p16 (second));
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poly16x8_t res1 = result.val[0], res2 = result.val[1];
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poly16_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
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poly16_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
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poly16x8_t expected1 = vld1q_p16 (exp1);
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poly16x8_t expected2 = vld1q_p16 (exp2);
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for (i = 0; i < 8; i++)
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if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
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abort ();
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return 0;
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}
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/* Test the `vzipq_p16' AArch64 SIMD intrinsic. */
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/* { dg-do run } */
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/* { dg-options "-save-temps -fno-inline" } */
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#include <arm_neon.h>
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#include "vzipqp16.x"
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/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
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/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
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/* { dg-final { cleanup-saved-temps } } */
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extern void abort (void);
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poly8x16x2_t
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test_vzipqp8 (poly8x16_t _a, poly8x16_t _b)
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{
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return vzipq_p8 (_a, _b);
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}
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int
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main (int argc, char **argv)
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{
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int i;
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poly8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
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poly8_t second[] =
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{17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
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poly8x16x2_t result = test_vzipqp8 (vld1q_p8 (first), vld1q_p8 (second));
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poly8x16_t res1 = result.val[0], res2 = result.val[1];
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poly8_t exp1[] = {1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23, 8, 24};
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poly8_t exp2[] =
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{9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31, 16, 32};
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poly8x16_t expected1 = vld1q_p8 (exp1);
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poly8x16_t expected2 = vld1q_p8 (exp2);
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for (i = 0; i < 16; i++)
|
||||
if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* Test the `vzipq_p8' AArch64 SIMD intrinsic. */
|
||||
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-save-temps -fno-inline" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "vzipqp8.x"
|
||||
|
||||
/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
extern void abort (void);
|
||||
|
||||
int16x8x2_t
|
||||
test_vzipqs16 (int16x8_t _a, int16x8_t _b)
|
||||
{
|
||||
return vzipq_s16 (_a, _b);
|
||||
}
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
int i;
|
||||
int16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
|
||||
int16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
|
||||
int16x8x2_t result = test_vzipqs16 (vld1q_s16 (first), vld1q_s16 (second));
|
||||
int16x8_t res1 = result.val[0], res2 = result.val[1];
|
||||
int16_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
|
||||
int16_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
|
||||
int16x8_t expected1 = vld1q_s16 (exp1);
|
||||
int16x8_t expected2 = vld1q_s16 (exp2);
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* Test the `vzipq_s16' AArch64 SIMD intrinsic. */
|
||||
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-save-temps -fno-inline" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "vzipqs16.x"
|
||||
|
||||
/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
extern void abort (void);
|
||||
|
||||
int32x4x2_t
|
||||
test_vzipqs32 (int32x4_t _a, int32x4_t _b)
|
||||
{
|
||||
return vzipq_s32 (_a, _b);
|
||||
}
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
int i;
|
||||
int32_t first[] = {1, 2, 3, 4};
|
||||
int32_t second[] = {5, 6, 7, 8};
|
||||
int32x4x2_t result = test_vzipqs32 (vld1q_s32 (first), vld1q_s32 (second));
|
||||
int32x4_t res1 = result.val[0], res2 = result.val[1];
|
||||
int32_t exp1[] = {1, 5, 2, 6};
|
||||
int32_t exp2[] = {3, 7, 4, 8};
|
||||
int32x4_t expected1 = vld1q_s32 (exp1);
|
||||
int32x4_t expected2 = vld1q_s32 (exp2);
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* Test the `vzipq_s32' AArch64 SIMD intrinsic. */
|
||||
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-save-temps -fno-inline" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "vzipqs32.x"
|
||||
|
||||
/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
extern void abort (void);
|
||||
|
||||
int8x16x2_t
|
||||
test_vzipqs8 (int8x16_t _a, int8x16_t _b)
|
||||
{
|
||||
return vzipq_s8 (_a, _b);
|
||||
}
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
int i;
|
||||
int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
|
||||
int8_t second[] =
|
||||
{17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
|
||||
int8x16x2_t result = test_vzipqs8 (vld1q_s8 (first), vld1q_s8 (second));
|
||||
int8x16_t res1 = result.val[0], res2 = result.val[1];
|
||||
int8_t exp1[] = {1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23, 8, 24};
|
||||
int8_t exp2[] =
|
||||
{9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31, 16, 32};
|
||||
int8x16_t expected1 = vld1q_s8 (exp1);
|
||||
int8x16_t expected2 = vld1q_s8 (exp2);
|
||||
|
||||
for (i = 0; i < 16; i++)
|
||||
if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* Test the `vzipq_s8' AArch64 SIMD intrinsic. */
|
||||
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-save-temps -fno-inline" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "vzipqs8.x"
|
||||
|
||||
/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
extern void abort (void);
|
||||
|
||||
uint16x8x2_t
|
||||
test_vzipqu16 (uint16x8_t _a, uint16x8_t _b)
|
||||
{
|
||||
return vzipq_u16 (_a, _b);
|
||||
}
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
int i;
|
||||
uint16_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
|
||||
uint16_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
|
||||
uint16x8x2_t result = test_vzipqu16 (vld1q_u16 (first), vld1q_u16 (second));
|
||||
uint16x8_t res1 = result.val[0], res2 = result.val[1];
|
||||
uint16_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
|
||||
uint16_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
|
||||
uint16x8_t expected1 = vld1q_u16 (exp1);
|
||||
uint16x8_t expected2 = vld1q_u16 (exp2);
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* Test the `vzipq_u16' AArch64 SIMD intrinsic. */
|
||||
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-save-temps -fno-inline" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "vzipqu16.x"
|
||||
|
||||
/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8h, ?v\[0-9\]+\.8h, ?v\[0-9\]+\.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
extern void abort (void);
|
||||
|
||||
uint32x4x2_t
|
||||
test_vzipqu32 (uint32x4_t _a, uint32x4_t _b)
|
||||
{
|
||||
return vzipq_u32 (_a, _b);
|
||||
}
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
int i;
|
||||
uint32_t first[] = {1, 2, 3, 4};
|
||||
uint32_t second[] = {5, 6, 7, 8};
|
||||
uint32x4x2_t result = test_vzipqu32 (vld1q_u32 (first), vld1q_u32 (second));
|
||||
uint32x4_t res1 = result.val[0], res2 = result.val[1];
|
||||
uint32_t exp1[] = {1, 5, 2, 6};
|
||||
uint32_t exp2[] = {3, 7, 4, 8};
|
||||
uint32x4_t expected1 = vld1q_u32 (exp1);
|
||||
uint32x4_t expected2 = vld1q_u32 (exp2);
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* Test the `vzipq_u32' AArch64 SIMD intrinsic. */
|
||||
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-save-temps -fno-inline" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "vzipqu32.x"
|
||||
|
||||
/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4s, ?v\[0-9\]+\.4s, ?v\[0-9\]+\.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
extern void abort (void);
|
||||
|
||||
uint8x16x2_t
|
||||
test_vzipqu8 (uint8x16_t _a, uint8x16_t _b)
|
||||
{
|
||||
return vzipq_u8 (_a, _b);
|
||||
}
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
int i;
|
||||
uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
|
||||
uint8_t second[] =
|
||||
{17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32};
|
||||
uint8x16x2_t result = test_vzipqu8 (vld1q_u8 (first), vld1q_u8 (second));
|
||||
uint8x16_t res1 = result.val[0], res2 = result.val[1];
|
||||
uint8_t exp1[] = {1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23, 8, 24};
|
||||
uint8_t exp2[] =
|
||||
{9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31, 16, 32};
|
||||
uint8x16_t expected1 = vld1q_u8 (exp1);
|
||||
uint8x16_t expected2 = vld1q_u8 (exp2);
|
||||
|
||||
for (i = 0; i < 16; i++)
|
||||
if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* Test the `vzipq_u8' AArch64 SIMD intrinsic. */
|
||||
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-save-temps -fno-inline" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "vzipqu8.x"
|
||||
|
||||
/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.16b, ?v\[0-9\]+\.16b, ?v\[0-9\]+\.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
extern void abort (void);
|
||||
|
||||
int16x4x2_t
|
||||
test_vzips16 (int16x4_t _a, int16x4_t _b)
|
||||
{
|
||||
return vzip_s16 (_a, _b);
|
||||
}
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
int i;
|
||||
int16_t first[] = {1, 2, 3, 4};
|
||||
int16_t second[] = {5, 6, 7, 8};
|
||||
int16x4x2_t result = test_vzips16 (vld1_s16 (first), vld1_s16 (second));
|
||||
int16x4_t res1 = result.val[0], res2 = result.val[1];
|
||||
int16_t exp1[] = {1, 5, 2, 6};
|
||||
int16_t exp2[] = {3, 7, 4, 8};
|
||||
int16x4_t expected1 = vld1_s16 (exp1);
|
||||
int16x4_t expected2 = vld1_s16 (exp2);
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* Test the `vzip_s16' AArch64 SIMD intrinsic. */
|
||||
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-save-temps -fno-inline" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "vzips16.x"
|
||||
|
||||
/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
extern void abort (void);
|
||||
|
||||
int32x2x2_t
|
||||
test_vzips32 (int32x2_t _a, int32x2_t _b)
|
||||
{
|
||||
return vzip_s32 (_a, _b);
|
||||
}
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
int i;
|
||||
int32_t first[] = {1, 2};
|
||||
int32_t second[] = {3, 4};
|
||||
int32x2x2_t result = test_vzips32 (vld1_s32 (first), vld1_s32 (second));
|
||||
int32x2_t res1 = result.val[0], res2 = result.val[1];
|
||||
int32_t exp1[] = {1, 3};
|
||||
int32_t exp2[] = {2, 4};
|
||||
int32x2_t expected1 = vld1_s32 (exp1);
|
||||
int32x2_t expected2 = vld1_s32 (exp2);
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* Test the `vzip_s32' AArch64 SIMD intrinsic. */
|
||||
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-save-temps -fno-inline" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "vzips32.x"
|
||||
|
||||
/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
extern void abort (void);
|
||||
|
||||
int8x8x2_t
|
||||
test_vzips8 (int8x8_t _a, int8x8_t _b)
|
||||
{
|
||||
return vzip_s8 (_a, _b);
|
||||
}
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
int i;
|
||||
int8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
|
||||
int8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
|
||||
int8x8x2_t result = test_vzips8 (vld1_s8 (first), vld1_s8 (second));
|
||||
int8x8_t res1 = result.val[0], res2 = result.val[1];
|
||||
int8_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
|
||||
int8_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
|
||||
int8x8_t expected1 = vld1_s8 (exp1);
|
||||
int8x8_t expected2 = vld1_s8 (exp2);
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* Test the `vzip_s8' AArch64 SIMD intrinsic. */
|
||||
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-save-temps -fno-inline" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "vzips8.x"
|
||||
|
||||
/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
extern void abort (void);
|
||||
|
||||
uint16x4x2_t
|
||||
test_vzipu16 (uint16x4_t _a, uint16x4_t _b)
|
||||
{
|
||||
return vzip_u16 (_a, _b);
|
||||
}
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
int i;
|
||||
uint16_t first[] = {1, 2, 3, 4};
|
||||
uint16_t second[] = {5, 6, 7, 8};
|
||||
uint16x4x2_t result = test_vzipu16 (vld1_u16 (first), vld1_u16 (second));
|
||||
uint16x4_t res1 = result.val[0], res2 = result.val[1];
|
||||
uint16_t exp1[] = {1, 5, 2, 6};
|
||||
uint16_t exp2[] = {3, 7, 4, 8};
|
||||
uint16x4_t expected1 = vld1_u16 (exp1);
|
||||
uint16x4_t expected2 = vld1_u16 (exp2);
|
||||
|
||||
for (i = 0; i < 4; i++)
|
||||
if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* Test the `vzip_u16' AArch64 SIMD intrinsic. */
|
||||
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-save-temps -fno-inline" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "vzipu16.x"
|
||||
|
||||
/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.4h, ?v\[0-9\]+\.4h, ?v\[0-9\]+\.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
extern void abort (void);
|
||||
|
||||
uint32x2x2_t
|
||||
test_vzipu32 (uint32x2_t _a, uint32x2_t _b)
|
||||
{
|
||||
return vzip_u32 (_a, _b);
|
||||
}
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
int i;
|
||||
uint32_t first[] = {1, 2};
|
||||
uint32_t second[] = {3, 4};
|
||||
uint32x2x2_t result = test_vzipu32 (vld1_u32 (first), vld1_u32 (second));
|
||||
uint32x2_t res1 = result.val[0], res2 = result.val[1];
|
||||
uint32_t exp1[] = {1, 3};
|
||||
uint32_t exp2[] = {2, 4};
|
||||
uint32x2_t expected1 = vld1_u32 (exp1);
|
||||
uint32x2_t expected2 = vld1_u32 (exp2);
|
||||
|
||||
for (i = 0; i < 2; i++)
|
||||
if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* Test the `vzip_u32' AArch64 SIMD intrinsic. */
|
||||
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-save-temps -fno-inline" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "vzipu32.x"
|
||||
|
||||
/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.2s, ?v\[0-9\]+\.2s, ?v\[0-9\]+\.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
extern void abort (void);
|
||||
|
||||
uint8x8x2_t
|
||||
test_vzipu8 (uint8x8_t _a, uint8x8_t _b)
|
||||
{
|
||||
return vzip_u8 (_a, _b);
|
||||
}
|
||||
|
||||
int
|
||||
main (int argc, char **argv)
|
||||
{
|
||||
int i;
|
||||
uint8_t first[] = {1, 2, 3, 4, 5, 6, 7, 8};
|
||||
uint8_t second[] = {9, 10, 11, 12, 13, 14, 15, 16};
|
||||
uint8x8x2_t result = test_vzipu8 (vld1_u8 (first), vld1_u8 (second));
|
||||
uint8x8_t res1 = result.val[0], res2 = result.val[1];
|
||||
uint8_t exp1[] = {1, 9, 2, 10, 3, 11, 4, 12};
|
||||
uint8_t exp2[] = {5, 13, 6, 14, 7, 15, 8, 16};
|
||||
uint8x8_t expected1 = vld1_u8 (exp1);
|
||||
uint8x8_t expected2 = vld1_u8 (exp2);
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
if ((res1[i] != expected1[i]) || (res2[i] != expected2[i]))
|
||||
abort ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* Test the `vzip_u8' AArch64 SIMD intrinsic. */
|
||||
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-save-temps -fno-inline" } */
|
||||
|
||||
#include <arm_neon.h>
|
||||
#include "vzipu8.x"
|
||||
|
||||
/* { dg-final { scan-assembler-times "zip1\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "zip2\[ \t\]+v\[0-9\]+\.8b, ?v\[0-9\]+\.8b, ?v\[0-9\]+\.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
|
||||
/* { dg-final { cleanup-saved-temps } } */
|
||||
Loading…
Reference in New Issue