re PR target/39715 ([cond-optab] extra sign extensions on Thumb)
2009-10-28 Paolo Bonzini <bonzini@gnu.org> PR rtl-optimization/39715 * combine.c (simplify_comparison): Use extensions to widen comparisons. Try an ANDing first. testsuite: 2009-10-28 Paolo Bonzini <bonzini@gnu.org> PR rtl-optimization/39715 * gcc.target/arm/thumb-bitfld1.c: New. From-SVN: r153651
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2009-10-28 Paolo Bonzini <bonzini@gnu.org>
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PR rtl-optimization/39715
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* combine.c (simplify_comparison): Use extensions to
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widen comparisons. Try an ANDing first.
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2009-10-28 Paolo Bonzini <bonzini@gnu.org>
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2009-10-28 Paolo Bonzini <bonzini@gnu.org>
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PR rtl-optimization/40741
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PR rtl-optimization/40741
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@ -11467,6 +11467,22 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
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{
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{
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int zero_extended;
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int zero_extended;
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/* If this is a test for negative, we can make an explicit
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test of the sign bit. Test this first so we can use
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a paradoxical subreg to extend OP0. */
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if (op1 == const0_rtx && (code == LT || code == GE)
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&& GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
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{
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op0 = simplify_gen_binary (AND, tmode,
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gen_lowpart (tmode, op0),
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GEN_INT ((HOST_WIDE_INT) 1
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<< (GET_MODE_BITSIZE (mode)
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- 1)));
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code = (code == LT) ? NE : EQ;
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break;
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}
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/* If the only nonzero bits in OP0 and OP1 are those in the
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/* If the only nonzero bits in OP0 and OP1 are those in the
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narrower mode and this is an equality or unsigned comparison,
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narrower mode and this is an equality or unsigned comparison,
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we can use the wider mode. Similarly for sign-extended
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we can use the wider mode. Similarly for sign-extended
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@ -11497,27 +11513,20 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
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XEXP (op0, 0)),
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XEXP (op0, 0)),
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gen_lowpart (tmode,
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gen_lowpart (tmode,
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XEXP (op0, 1)));
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XEXP (op0, 1)));
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else
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op0 = gen_lowpart (tmode, op0);
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{
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if (zero_extended && CONST_INT_P (op1))
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if (zero_extended)
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op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
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{
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op1 = gen_lowpart (tmode, op1);
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op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
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op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
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}
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else
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{
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op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
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op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
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}
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break;
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break;
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}
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}
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/* If this is a test for negative, we can make an explicit
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test of the sign bit. */
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if (op1 == const0_rtx && (code == LT || code == GE)
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&& GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
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{
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op0 = simplify_gen_binary (AND, tmode,
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gen_lowpart (tmode, op0),
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GEN_INT ((HOST_WIDE_INT) 1
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<< (GET_MODE_BITSIZE (mode)
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- 1)));
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code = (code == LT) ? NE : EQ;
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break;
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}
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}
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}
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}
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@ -1,3 +1,8 @@
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2009-10-28 Paolo Bonzini <bonzini@gnu.org>
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PR rtl-optimization/39715
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* gcc.target/arm/thumb-bitfld1.c: New.
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2009-10-28 Paolo Bonzini <bonzini@gnu.org>
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2009-10-28 Paolo Bonzini <bonzini@gnu.org>
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PR rtl-optimization/40741
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PR rtl-optimization/40741
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@ -0,0 +1,19 @@
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/* { dg-do compile } */
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/* { dg-options "-O1 -mthumb -march=armv5t" } */
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struct foo
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{
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unsigned b31 : 1;
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unsigned b30 : 1;
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unsigned b29 : 1;
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unsigned b28 : 1;
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unsigned rest : 28;
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};
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foo(a)
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struct foo a;
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{
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return a.b30;
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}
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/* { dg-final { scan-assembler-times "lsl" 1 } } */
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/* { dg-final { scan-assembler-times "lsr" 1 } } */
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