driver-i386.c (host_detect_local_cpu): Detect cascadelake.
gcc/ChangeLog 2018-12-18 Wei Xiao <wei3.xiao@intel.com> * config/i386/driver-i386.c (host_detect_local_cpu): Detect cascadelake. * config/i386/i386.c (fold_builtin_cpu): Handle cascadelake. * doc/extend.texi: Add cascadelake. gcc/testsuite/ChangeLog 2018-12-18 Wei Xiao <wei3.xiao@intel.com> * g++.target/i386/mv16.C: Handle new march. * gcc.target/i386/builtin_target.c: Ditto. libgcc/ChangeLog 2018-12-18 Wei Xiao <wei3.xiao@intel.com> * config/i386/cpuinfo.c (get_intel_cpu): Handle cascadelake. * config/i386/cpuinfo.h: Add INTEL_COREI7_CASCADELAKE. From-SVN: r267226
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@ -1,3 +1,8 @@
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2018-12-18 Wei Xiao <wei3.xiao@intel.com>
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* config/i386/driver-i386.c (host_detect_local_cpu): Detect cascadelake.
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* config/i386/i386.c (fold_builtin_cpu): Handle cascadelake.
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* doc/extend.texi: Add cascadelake.
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2018-12-17 Peter Bergner <bergner@linux.ibm.com>
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2018-12-17 Peter Bergner <bergner@linux.ibm.com>
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PR target/87870
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PR target/87870
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@ -832,6 +832,10 @@ const char *host_detect_local_cpu (int argc, const char **argv)
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cpu = "skylake";
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cpu = "skylake";
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break;
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break;
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case 0x55:
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case 0x55:
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if (has_avx512vnni)
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/* Cascade Lake. */
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cpu = "cascadelake";
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else
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/* Skylake with AVX-512. */
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/* Skylake with AVX-512. */
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cpu = "skylake-avx512";
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cpu = "skylake-avx512";
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break;
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break;
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@ -32393,7 +32393,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
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M_INTEL_COREI7_CANNONLAKE,
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M_INTEL_COREI7_CANNONLAKE,
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M_INTEL_COREI7_ICELAKE_CLIENT,
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M_INTEL_COREI7_ICELAKE_CLIENT,
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M_INTEL_COREI7_ICELAKE_SERVER,
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M_INTEL_COREI7_ICELAKE_SERVER,
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M_AMDFAM17H_ZNVER2
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M_AMDFAM17H_ZNVER2,
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M_INTEL_COREI7_CASCADELAKE
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};
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};
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static struct _arch_names_table
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static struct _arch_names_table
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@ -32420,6 +32421,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
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{"cannonlake", M_INTEL_COREI7_CANNONLAKE},
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{"cannonlake", M_INTEL_COREI7_CANNONLAKE},
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{"icelake-client", M_INTEL_COREI7_ICELAKE_CLIENT},
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{"icelake-client", M_INTEL_COREI7_ICELAKE_CLIENT},
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{"icelake-server", M_INTEL_COREI7_ICELAKE_SERVER},
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{"icelake-server", M_INTEL_COREI7_ICELAKE_SERVER},
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{"cascadelake", M_INTEL_COREI7_CASCADELAKE},
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{"bonnell", M_INTEL_BONNELL},
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{"bonnell", M_INTEL_BONNELL},
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{"silvermont", M_INTEL_SILVERMONT},
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{"silvermont", M_INTEL_SILVERMONT},
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{"goldmont", M_INTEL_GOLDMONT},
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{"goldmont", M_INTEL_GOLDMONT},
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@ -20768,6 +20768,9 @@ Intel Core i7 Ice Lake Client CPU.
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@item icelake-server
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@item icelake-server
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Intel Core i7 Ice Lake Server CPU.
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Intel Core i7 Ice Lake Server CPU.
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@item cascadelake
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Intel Core i7 Cascadelake CPU.
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@item bonnell
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@item bonnell
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Intel Atom Bonnell CPU.
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Intel Atom Bonnell CPU.
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@ -1,3 +1,8 @@
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2018-12-18 Wei Xiao <wei3.xiao@intel.com>
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* g++.target/i386/mv16.C: Handle new march.
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* gcc.target/i386/builtin_target.c: Ditto.
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2018-12-17 Peter Bergner <bergner@linux.ibm.com>
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2018-12-17 Peter Bergner <bergner@linux.ibm.com>
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PR target/87870
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PR target/87870
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@ -68,6 +68,10 @@ int __attribute__ ((target("arch=icelake-server"))) foo () {
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return 18;
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return 18;
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}
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}
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int __attribute__ ((target("arch=cascadelake"))) foo () {
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return 19;
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}
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int main ()
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int main ()
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{
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{
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int val = foo ();
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int val = foo ();
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@ -94,6 +98,8 @@ int main ()
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assert (val == 17);
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assert (val == 17);
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else if (__builtin_cpu_is ("icelake-server"))
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else if (__builtin_cpu_is ("icelake-server"))
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assert (val == 18);
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assert (val == 18);
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else if (__builtin_cpu_is ("cascadelake"))
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assert (val == 19);
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else
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else
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assert (val == 0);
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assert (val == 0);
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@ -108,10 +108,18 @@ check_intel_cpu_model (unsigned int family, unsigned int model,
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assert (__builtin_cpu_is ("skylake"));
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assert (__builtin_cpu_is ("skylake"));
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break;
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break;
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case 0x55:
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case 0x55:
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/* Skylake with AVX-512 support. */
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{
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unsigned int eax, ebx, ecx, edx;
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__cpuid_count (7, 0, eax, ebx, ecx, edx);
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assert (__builtin_cpu_is ("corei7"));
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assert (__builtin_cpu_is ("corei7"));
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if (ecx & bit_AVX512VNNI)
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/* Cascade Lake. */
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assert (__builtin_cpu_is ("cascadelake"));
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else
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/* Skylake with AVX-512 support. */
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assert (__builtin_cpu_is ("skylake-avx512"));
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assert (__builtin_cpu_is ("skylake-avx512"));
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break;
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break;
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}
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case 0x66:
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case 0x66:
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/* Cannon Lake. */
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/* Cannon Lake. */
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assert (__builtin_cpu_is ("cannonlake"));
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assert (__builtin_cpu_is ("cannonlake"));
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@ -1,3 +1,8 @@
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2018-12-18 Wei Xiao <wei3.xiao@intel.com>
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* config/i386/cpuinfo.c (get_intel_cpu): Handle cascadelake.
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* config/i386/cpuinfo.h: Add INTEL_COREI7_CASCADELAKE.
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2018-12-12 Rasmus Villemoes <rv@rasmusvillemoes.dk>
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2018-12-12 Rasmus Villemoes <rv@rasmusvillemoes.dk>
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* config/rs6000/tramp.S (__trampoline_setup): Also emit .size
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* config/rs6000/tramp.S (__trampoline_setup): Also emit .size
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@ -215,9 +215,17 @@ get_intel_cpu (unsigned int family, unsigned int model, unsigned int brand_id)
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__cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE;
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__cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE;
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break;
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break;
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case 0x55:
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case 0x55:
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/* Skylake with AVX-512 support. */
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{
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unsigned int eax, ebx, ecx, edx;
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__cpu_model.__cpu_type = INTEL_COREI7;
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__cpu_model.__cpu_type = INTEL_COREI7;
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__cpuid_count (7, 0, eax, ebx, ecx, edx);
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if (ecx & bit_AVX512VNNI)
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/* Cascade Lake. */
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__cpu_model.__cpu_subtype = INTEL_COREI7_CASCADELAKE;
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else
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/* Skylake with AVX-512 support. */
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__cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE_AVX512;
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__cpu_model.__cpu_subtype = INTEL_COREI7_SKYLAKE_AVX512;
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}
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break;
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break;
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case 0x66:
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case 0x66:
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/* Cannon Lake. */
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/* Cannon Lake. */
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@ -76,6 +76,7 @@ enum processor_subtypes
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INTEL_COREI7_ICELAKE_CLIENT,
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INTEL_COREI7_ICELAKE_CLIENT,
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INTEL_COREI7_ICELAKE_SERVER,
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INTEL_COREI7_ICELAKE_SERVER,
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AMDFAM17H_ZNVER2,
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AMDFAM17H_ZNVER2,
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INTEL_COREI7_CASCADELAKE,
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CPU_SUBTYPE_MAX
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CPU_SUBTYPE_MAX
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};
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};
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