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install.texi (--with-cpu): Mention ARC. 

2013-10-01  Joern Rennecke  <joern.rennecke@embecosm.com>
            Jeremy Bennett  <jeremy.bennett@embecosm.com>

        * doc/install.texi (--with-cpu): Mention ARC.
        (arc-*-elf32): New paragraph.
        (arc-linux-uclibc): Likewise.
        * doc/md.texi (Machine Constraints): Add ARC part.
        * doc/invoke.texi: (menu): Add ARC Options.
        (Machine Dependent Options) <ARC Options>: Add synopsis.
        (node ARC Options): Add.
        * doc/extend.texi (long_call / short_call attribute): Add ARC.
        (ARC Built-in Functions): New section defining
        generic ARC built-in functions.
        (ARC SIMD Built-in Functions): New section defining SIMD specific
        built-in functions.
        (Declaring Attributes of Functions): Extended
        description of short_call and long_call attributes for ARC and
        added index entries.


Co-Authored-By: Jeremy Bennett <jeremy.bennett@embecosm.com>

From-SVN: r203074
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Joern Rennecke 2013-10-01 17:29:40 +00:00 committed by Joern Rennecke
parent d38a64b4e0
commit 5d5f672027
5 changed files with 1072 additions and 9 deletions
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gcc/ChangeLog
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@ -1,3 +1,22 @@
2013-10-01 Joern Rennecke <joern.rennecke@embecosm.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
* doc/install.texi (--with-cpu): Mention ARC.
(arc-*-elf32): New paragraph.
(arc-linux-uclibc): Likewise.
* doc/md.texi (Machine Constraints): Add ARC part.
* doc/invoke.texi: (menu): Add ARC Options.
(Machine Dependent Options) <ARC Options>: Add synopsis.
(node ARC Options): Add.
* doc/extend.texi (long_call / short_call attribute): Add ARC.
(ARC Built-in Functions): New section defining
generic ARC built-in functions.
(ARC SIMD Built-in Functions): New section defining SIMD specific
built-in functions.
(Declaring Attributes of Functions): Extended
description of short_call and long_call attributes for ARC and
added index entries.
2013-10-01 Saurabh Verma <saurabh.verma@codito.com>
Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
Joern Rennecke <joern.rennecke@embecosm.com>

469
gcc/doc/extend.texi
View File

@ -2813,8 +2813,9 @@ least version 2.20.1), and GNU C library (at least version 2.11.1).
@item interrupt
@cindex interrupt handler functions
Use this attribute on the ARM, AVR, CR16, Epiphany, M32C, M32R/D, m68k, MeP, MIPS,
MSP430, RL78, RX and Xstormy16 ports to indicate that the specified function is an
Use this attribute on the ARC, ARM, AVR, CR16, Epiphany, M32C, M32R/D,
m68k, MeP, MIPS, MSP430, RL78, RX and Xstormy16 ports to indicate that
the specified function is an
interrupt handler. The compiler generates function entry and exit
sequences suitable for use in an interrupt handler when this attribute
is present. With Epiphany targets it may also generate a special section with
@ -2823,6 +2824,16 @@ code to initialize the interrupt vector table.
Note, interrupt handlers for the Blackfin, H8/300, H8/300H, H8S, MicroBlaze,
and SH processors can be specified via the @code{interrupt_handler} attribute.
Note, on the ARC, you must specify the kind of interrupt to be handled
in a parameter to the interrupt attribute like this:
@smallexample
void f () __attribute__ ((interrupt ("ilink1")));
@end smallexample
Permissible values for this parameter are: @w{@code{ilink1}} and
@w{@code{ilink2}}.
Note, on the AVR, the hardware globally disables interrupts when an
interrupt is executed. The first instruction of an interrupt handler
declared with this attribute is a @code{SEI} instruction to
@ -3021,18 +3032,33 @@ unit. This is to allow easy merging of multiple compilation units into one,
for example, by using the link-time optimization. For this reason the
attribute is not allowed on types to annotate indirect calls.
@item long_call/short_call
@item long_call/medium_call/short_call
@cindex indirect calls on ARC
@cindex indirect calls on ARM
This attribute specifies how a particular function is called on
ARM and Epiphany. Both attributes override the
@option{-mlong-calls} (@pxref{ARM Options})
command-line switch and @code{#pragma long_calls} settings. The
@cindex indirect calls on Epiphany
These attribute specifies how a particular function is called on
ARC, ARM and Epiphany - with @code{medium_call} being specific to ARC.
These attributes override the
@option{-mlong-calls} (@pxref{ARM Options} and @ref{ARC Options})
and @option{-mmedium-calls} (@pxref{ARC Options})
command-line switches and @code{#pragma long_calls} settings. For ARM, the
@code{long_call} attribute indicates that the function might be far
away from the call site and require a different (more expensive)
calling sequence. The @code{short_call} attribute always places
the offset to the function from the call site into the @samp{BL}
instruction directly.
For ARC, a function marked with the @code{long_call} attribute is
always called using register-indirect jump-and-link instructions,
thereby enabling the called function to be placed anywhere within the
32-bit address space. A function marked with the @code{medium_call}
attribute will always be close enough to be called with an unconditional
branch-and-link instruction, which has a 25-bit offset from
the call site. A function marked with the @code{short_call}
attribute will always be close enough to be called with a conditional
branch-and-link instruction, which has a 21-bit offset from
the call site.
@item longcall/shortcall
@cindex functions called via pointer on the RS/6000 and PowerPC
On the Blackfin, RS/6000 and PowerPC, the @code{longcall} attribute
@ -8870,6 +8896,8 @@ instructions, but allow the compiler to schedule those calls.
@menu
* Alpha Built-in Functions::
* ARC Built-in Functions::
* ARC SIMD Built-in Functions::
* ARM iWMMXt Built-in Functions::
* ARM NEON Intrinsics::
* AVR Built-in Functions::
@ -8977,6 +9005,430 @@ void *__builtin_thread_pointer (void)
void __builtin_set_thread_pointer (void *)
@end smallexample
@node ARC Built-in Functions
@subsection ARC Built-in Functions
The following built-in functions are provided for ARC targets. The
built-ins generate the corresponding assembly instructions. In the
examples given below, the generated code often requires an operand or
result to be in a register. Where necessary further code will be
generated to ensure this is true, but for brevity this is not
described in each case.
@emph{Note:} Using a built-in to generate an instruction not supported
by a target may cause problems. At present the compiler is not
guaranteed to detect such misuse, and as a result an internal compiler
error may be generated.
@deftypefn {Built-in Function} int __builtin_arc_aligned (void *@var{val}, int @var{alignval})
Return 1 if @var{val} is known to have the byte alignment given
by @var{alignval}, otherwise return 0.
Note that this is different from
@smallexample
__alignof__(*(char *)@var{val}) >= alignval
@end smallexample
because __alignof__ sees only the type of the dereference, wheras
__builtin_arc_align uses alignment information from the pointer
as well as from the pointed-to type.
The information available will depend on optimization level.
@end deftypefn
@deftypefn {Built-in Function} void __builtin_arc_brk (void)
Generates
@example
brk
@end example
@end deftypefn
@deftypefn {Built-in Function} {unsigned int} __builtin_arc_core_read (unsigned int @var{regno})
The operand is the number of a register to be read. Generates:
@example
mov @var{dest}, r@var{regno}
@end example
where the value in @var{dest} will be the result returned from the
built-in.
@end deftypefn
@deftypefn {Built-in Function} void __builtin_arc_core_write (unsigned int @var{regno}, unsigned int @var{val})
The first operand is the number of a register to be written, the
second operand is a compile time constant to write into that
register. Generates:
@example
mov r@var{regno}, @var{val}
@end example
@end deftypefn
@deftypefn {Built-in Function} int __builtin_arc_divaw (int @var{a}, int @var{b})
Only available if either @option{-mcpu=ARC700} or @option{-meA} is set.
Generates:
@example
divaw @var{dest}, @var{a}, @var{b}
@end example
where the value in @var{dest} will be the result returned from the
built-in.
@end deftypefn
@deftypefn {Built-in Function} void __builtin_arc_flag (unsigned int @var{a})
Generates
@example
flag @var{a}
@end example
@end deftypefn
@deftypefn {Built-in Function} {unsigned int} __builtin_arc_lr (unsigned int @var{auxr})
The operand, @var{auxv}, is the address of an auxiliary register and
must be a compile time constant. Generates:
@example
lr @var{dest}, [@var{auxr}]
@end example
Where the value in @var{dest} will be the result returned from the
built-in.
@end deftypefn
@deftypefn {Built-in Function} void __builtin_arc_mul64 (int @var{a}, int @var{b})
Only available with @option{-mmul64}. Generates:
@example
mul64 @var{a}, @var{b}
@end example
@end deftypefn
@deftypefn {Built-in Function} void __builtin_arc_mulu64 (unsigned int @var{a}, unsigned int @var{b})
Only available with @option{-mmul64}. Generates:
@example
mulu64 @var{a}, @var{b}
@end example
@end deftypefn
@deftypefn {Built-in Function} void __builtin_arc_nop (void)
Generates:
@example
nop
@end example
@end deftypefn
@deftypefn {Built-in Function} int __builtin_arc_norm (int @var{src})
Only valid if the @samp{norm} instruction is available through the
@option{-mnorm} option or by default with @option{-mcpu=ARC700}.
Generates:
@example
norm @var{dest}, @var{src}
@end example
Where the value in @var{dest} will be the result returned from the
built-in.
@end deftypefn
@deftypefn {Built-in Function} {short int} __builtin_arc_normw (short int @var{src})
Only valid if the @samp{normw} instruction is available through the
@option{-mnorm} option or by default with @option{-mcpu=ARC700}.
Generates:
@example
normw @var{dest}, @var{src}
@end example
Where the value in @var{dest} will be the result returned from the
built-in.
@end deftypefn
@deftypefn {Built-in Function} void __builtin_arc_rtie (void)
Generates:
@example
rtie
@end example
@end deftypefn
@deftypefn {Built-in Function} void __builtin_arc_sleep (int @var{a}
Generates:
@example
sleep @var{a}
@end example
@end deftypefn
@deftypefn {Built-in Function} void __builtin_arc_sr (unsigned int @var{auxr}, unsigned int @var{val})
The first argument, @var{auxv}, is the address of an auxiliary
register, the second argument, @var{val}, is a compile time constant
to be written to the register. Generates:
@example
sr @var{auxr}, [@var{val}]
@end example
@end deftypefn
@deftypefn {Built-in Function} int __builtin_arc_swap (int @var{src})
Only valid with @option{-mswap}. Generates:
@example
swap @var{dest}, @var{src}
@end example
Where the value in @var{dest} will be the result returned from the
built-in.
@end deftypefn
@deftypefn {Built-in Function} void __builtin_arc_swi (void)
Generates:
@example
swi
@end example
@end deftypefn
@deftypefn {Built-in Function} void __builtin_arc_sync (void)
Only available with @option{-mcpu=ARC700}. Generates:
@example
sync
@end example
@end deftypefn
@deftypefn {Built-in Function} void __builtin_arc_trap_s (unsigned int @var{c})
Only available with @option{-mcpu=ARC700}. Generates:
@example
trap_s @var{c}
@end example
@end deftypefn
@deftypefn {Built-in Function} void __builtin_arc_unimp_s (void)
Only available with @option{-mcpu=ARC700}. Generates:
@example
unimp_s
@end example
@end deftypefn
The instructions generated by the following builtins are not
considered as candidates for scheduling. They are not moved around by
the compiler during scheduling, and thus can be expected to appear
where they are put in the C code:
@example
__builtin_arc_brk()
__builtin_arc_core_read()
__builtin_arc_core_write()
__builtin_arc_flag()
__builtin_arc_lr()
__builtin_arc_sleep()
__builtin_arc_sr()
__builtin_arc_swi()
@end example
@node ARC SIMD Built-in Functions
@subsection ARC SIMD Built-in Functions
SIMD builtins provided by the compiler can be used to generate the
vector instructions. This section describes the available builtins
and their usage in programs. With the @option{-msimd} option, the
compiler provides 128-bit vector types, which can be specified using
the @code{vector_size} attribute. The header file @file{arc-simd.h}
can be included to use the following predefined types:
@example
typedef int __v4si __attribute__((vector_size(16)));
typedef short __v8hi __attribute__((vector_size(16)));
@end example
These types can be used to define 128-bit variables. The built-in
functions listed in the following section can be used on these
variables to generate the vector operations.
For all builtins, @code{__builtin_arc_@var{someinsn}}, the header file
@file{arc-simd.h} also provides equivalent macros called
@code{_@var{someinsn}} that can be used for programming ease and
improved readability. The following macros for DMA control are also
provided:
@example
#define _setup_dma_in_channel_reg _vdiwr
#define _setup_dma_out_channel_reg _vdowr
@end example
The following is a complete list of all the SIMD built-ins provided
for ARC, grouped by calling signature.
The following take two @code{__v8hi} arguments and return a
@code{__v8hi} result:
@example
__v8hi __builtin_arc_vaddaw (__v8hi, __v8hi)
__v8hi __builtin_arc_vaddw (__v8hi, __v8hi)
__v8hi __builtin_arc_vand (__v8hi, __v8hi)
__v8hi __builtin_arc_vandaw (__v8hi, __v8hi)
__v8hi __builtin_arc_vavb (__v8hi, __v8hi)
__v8hi __builtin_arc_vavrb (__v8hi, __v8hi)
__v8hi __builtin_arc_vbic (__v8hi, __v8hi)
__v8hi __builtin_arc_vbicaw (__v8hi, __v8hi)
__v8hi __builtin_arc_vdifaw (__v8hi, __v8hi)
__v8hi __builtin_arc_vdifw (__v8hi, __v8hi)
__v8hi __builtin_arc_veqw (__v8hi, __v8hi)
__v8hi __builtin_arc_vh264f (__v8hi, __v8hi)
__v8hi __builtin_arc_vh264ft (__v8hi, __v8hi)
__v8hi __builtin_arc_vh264fw (__v8hi, __v8hi)
__v8hi __builtin_arc_vlew (__v8hi, __v8hi)
__v8hi __builtin_arc_vltw (__v8hi, __v8hi)
__v8hi __builtin_arc_vmaxaw (__v8hi, __v8hi)
__v8hi __builtin_arc_vmaxw (__v8hi, __v8hi)
__v8hi __builtin_arc_vminaw (__v8hi, __v8hi)
__v8hi __builtin_arc_vminw (__v8hi, __v8hi)
__v8hi __builtin_arc_vmr1aw (__v8hi, __v8hi)
__v8hi __builtin_arc_vmr1w (__v8hi, __v8hi)
__v8hi __builtin_arc_vmr2aw (__v8hi, __v8hi)
__v8hi __builtin_arc_vmr2w (__v8hi, __v8hi)
__v8hi __builtin_arc_vmr3aw (__v8hi, __v8hi)
__v8hi __builtin_arc_vmr3w (__v8hi, __v8hi)
__v8hi __builtin_arc_vmr4aw (__v8hi, __v8hi)
__v8hi __builtin_arc_vmr4w (__v8hi, __v8hi)
__v8hi __builtin_arc_vmr5aw (__v8hi, __v8hi)
__v8hi __builtin_arc_vmr5w (__v8hi, __v8hi)
__v8hi __builtin_arc_vmr6aw (__v8hi, __v8hi)
__v8hi __builtin_arc_vmr6w (__v8hi, __v8hi)
__v8hi __builtin_arc_vmr7aw (__v8hi, __v8hi)
__v8hi __builtin_arc_vmr7w (__v8hi, __v8hi)
__v8hi __builtin_arc_vmrb (__v8hi, __v8hi)
__v8hi __builtin_arc_vmulaw (__v8hi, __v8hi)
__v8hi __builtin_arc_vmulfaw (__v8hi, __v8hi)
__v8hi __builtin_arc_vmulfw (__v8hi, __v8hi)
__v8hi __builtin_arc_vmulw (__v8hi, __v8hi)
__v8hi __builtin_arc_vnew (__v8hi, __v8hi)
__v8hi __builtin_arc_vor (__v8hi, __v8hi)
__v8hi __builtin_arc_vsubaw (__v8hi, __v8hi)
__v8hi __builtin_arc_vsubw (__v8hi, __v8hi)
__v8hi __builtin_arc_vsummw (__v8hi, __v8hi)
__v8hi __builtin_arc_vvc1f (__v8hi, __v8hi)
__v8hi __builtin_arc_vvc1ft (__v8hi, __v8hi)
__v8hi __builtin_arc_vxor (__v8hi, __v8hi)
__v8hi __builtin_arc_vxoraw (__v8hi, __v8hi)
@end example
The following take one @code{__v8hi} and one @code{int} argument and return a
@code{__v8hi} result:
@example
__v8hi __builtin_arc_vbaddw (__v8hi, int)
__v8hi __builtin_arc_vbmaxw (__v8hi, int)
__v8hi __builtin_arc_vbminw (__v8hi, int)
__v8hi __builtin_arc_vbmulaw (__v8hi, int)
__v8hi __builtin_arc_vbmulfw (__v8hi, int)
__v8hi __builtin_arc_vbmulw (__v8hi, int)
__v8hi __builtin_arc_vbrsubw (__v8hi, int)
__v8hi __builtin_arc_vbsubw (__v8hi, int)
@end example
The following take one @code{__v8hi} argument and one @code{int} argument which
must be a 3-bit compile time constant indicating a register number
I0-I7. They return a @code{__v8hi} result.
@example
__v8hi __builtin_arc_vasrw (__v8hi, const int)
__v8hi __builtin_arc_vsr8 (__v8hi, const int)
__v8hi __builtin_arc_vsr8aw (__v8hi, const int)
@end example
The following take one @code{__v8hi} argument and one @code{int}
argument which must be a 6-bit compile time constant. They return a
@code{__v8hi} result.
@example
__v8hi __builtin_arc_vasrpwbi (__v8hi, const int)
__v8hi __builtin_arc_vasrrpwbi (__v8hi, const int)
__v8hi __builtin_arc_vasrrwi (__v8hi, const int)
__v8hi __builtin_arc_vasrsrwi (__v8hi, const int)
__v8hi __builtin_arc_vasrwi (__v8hi, const int)
__v8hi __builtin_arc_vsr8awi (__v8hi, const int)
__v8hi __builtin_arc_vsr8i (__v8hi, const int)
@end example
The following take one @code{__v8hi} argument and one @code{int} argument which
must be a 8-bit compile time constant. They return a @code{__v8hi}
result.
@example
__v8hi __builtin_arc_vd6tapf (__v8hi, const int)
__v8hi __builtin_arc_vmvaw (__v8hi, const int)
__v8hi __builtin_arc_vmvw (__v8hi, const int)
__v8hi __builtin_arc_vmvzw (__v8hi, const int)
@end example
The following take two @code{int} arguments, the second of which which
must be a 8-bit compile time constant. They return a @code{__v8hi}
result:
@example
__v8hi __builtin_arc_vmovaw (int, const int)
__v8hi __builtin_arc_vmovw (int, const int)
__v8hi __builtin_arc_vmovzw (int, const int)
@end example
The following take a single @code{__v8hi} argument and return a
@code{__v8hi} result:
@example
__v8hi __builtin_arc_vabsaw (__v8hi)
__v8hi __builtin_arc_vabsw (__v8hi)
__v8hi __builtin_arc_vaddsuw (__v8hi)
__v8hi __builtin_arc_vexch1 (__v8hi)
__v8hi __builtin_arc_vexch2 (__v8hi)
__v8hi __builtin_arc_vexch4 (__v8hi)
__v8hi __builtin_arc_vsignw (__v8hi)
__v8hi __builtin_arc_vupbaw (__v8hi)
__v8hi __builtin_arc_vupbw (__v8hi)
__v8hi __builtin_arc_vupsbaw (__v8hi)
__v8hi __builtin_arc_vupsbw (__v8hi)
@end example
The followign take two @code{int} arguments and return no result:
@example
void __builtin_arc_vdirun (int, int)
void __builtin_arc_vdorun (int, int)
@end example
The following take two @code{int} arguments and return no result. The
first argument must a 3-bit compile time constant indicating one of
the DR0-DR7 DMA setup channels:
@example
void __builtin_arc_vdiwr (const int, int)
void __builtin_arc_vdowr (const int, int)
@end example
The following take an @code{int} argument and return no result:
@example
void __builtin_arc_vendrec (int)
void __builtin_arc_vrec (int)
void __builtin_arc_vrecrun (int)
void __builtin_arc_vrun (int)
@end example
The following take a @code{__v8hi} argument and two @code{int}
arguments and return a @code{__v8hi} result. The second argument must
be a 3-bit compile time constants, indicating one the registers I0-I7,
and the third argument must be an 8-bit compile time constant.
@emph{Note:} Although the equivalent hardware instructions do not take
an SIMD register as an operand, these builtins overwrite the relevant
bits of the @code{__v8hi} register provided as the first argument with
the value loaded from the @code{[Ib, u8]} location in the SDM.
@example
__v8hi __builtin_arc_vld32 (__v8hi, const int, const int)
__v8hi __builtin_arc_vld32wh (__v8hi, const int, const int)
__v8hi __builtin_arc_vld32wl (__v8hi, const int, const int)
__v8hi __builtin_arc_vld64 (__v8hi, const int, const int)
@end example
The following take two @code{int} arguments and return a @code{__v8hi}
result. The first argument must be a 3-bit compile time constants,
indicating one the registers I0-I7, and the second argument must be an
8-bit compile time constant.
@example
__v8hi __builtin_arc_vld128 (const int, const int)
__v8hi __builtin_arc_vld64w (const int, const int)
@end example
The following take a @code{__v8hi} argument and two @code{int}
arguments and return no result. The second argument must be a 3-bit
compile time constants, indicating one the registers I0-I7, and the
third argument must be an 8-bit compile time constant.
@example
void __builtin_arc_vst128 (__v8hi, const int, const int)
void __builtin_arc_vst64 (__v8hi, const int, const int)
@end example
The following take a @code{__v8hi} argument and three @code{int}
arguments and return no result. The second argument must be a 3-bit
compile-time constant, identifying the 16-bit sub-register to be
stored, the third argument must be a 3-bit compile time constants,
indicating one the registers I0-I7, and the fourth argument must be an
8-bit compile time constant.
@example
void __builtin_arc_vst16_n (__v8hi, const int, const int, const int)
void __builtin_arc_vst32_n (__v8hi, const int, const int, const int)
@end example
@node ARM iWMMXt Built-in Functions
@subsection ARM iWMMXt Built-in Functions
@ -16831,3 +17283,6 @@ implicitly scoped inside a C language scope. Also, an empty prototype
@code{()} is treated as an unspecified number of arguments, rather
than no arguments, as C++ demands.
@end table
@c LocalWords: emph deftypefn builtin ARCv2EM SIMD builtins msimd
@c LocalWords: typedef v4si v8hi DMA dma vdiwr vdowr followign

22
gcc/doc/install.texi
View File

@ -1200,8 +1200,8 @@ This is an alias for @option{--enable-tls=no}.
@itemx --with-cpu-64=@var{cpu}
Specify which cpu variant the compiler should generate code for by default.
@var{cpu} will be used as the default value of the @option{-mcpu=} switch.
This option is only supported on some targets, including ARM, i386, M68k,
PowerPC, and SPARC@. The @option{--with-cpu-32} and
This option is only supported on some targets, including ARC, ARM, i386, M68k,
PowerPC, and SPARC@. It is mandatory for ARC@. The @option{--with-cpu-32} and
@option{--with-cpu-64} options specify separate default CPUs for
32-bit and 64-bit modes; these options are only supported for i386,
x86-64 and PowerPC.
@ -3206,6 +3206,24 @@ are the versions which identify themselves as DEC OSF/1.)
@heading amd64-*-solaris2.1[0-9]*
This is a synonym for @samp{x86_64-*-solaris2.1[0-9]*}.
@html
<hr />
@end html
@anchor{arc-x-elf32}
@heading arc-*-elf32
Use @samp{configure --target=arc-elf32 --with-cpu=@var{cpu} --enable-languages="c,c++"}
to configure GCC, with @var{cpu} being one of @samp{arc600}, @samp{arc601},
or @samp{arc700}@.
@html
<hr />
@end html
@anchor{arc-linux-uclibc}
@heading arc-linux-uclibc
Use @samp{configure --target=arc-linux-uclibc --with-cpu=arc700 --enable-languages="c,c++"} to configure GCC@.
@html
<hr />
@end html

523
gcc/doc/invoke.texi
View File

@ -490,6 +490,23 @@ Objective-C and Objective-C++ Dialects}.
-mfp-mode=@var{mode} -mvect-double -max-vect-align=@var{num} @gol
-msplit-vecmove-early -m1reg-@var{reg}}
@emph{ARC Options}
@gccoptlist{-mbarrel-shifter @gol
-mcpu=@var{cpu} -mA6 -mARC600 -mA7 -mARC700 @gol
-mdpfp -mdpfp-compact -mdpfp-fast -mno-dpfp-lrsr @gol
-mea -mno-mpy -mmul32x16 -mmul64 @gol
-mnorm -mspfp -mspfp-compact -mspfp-fast -msimd -msoft-float -mswap @gol
-mcrc -mdsp-packa -mdvbf -mlock -mmac-d16 -mmac-24 -mrtsc -mswape @gol
-mtelephony -mxy -misize -mannotate-align -marclinux -marclinux_prof @gol
-mepilogue-cfi -mlong-calls -mmedium-calls -msdata @gol
-mucb-mcount -mvolatile-cache @gol
-malign-call -mauto-modify-reg -mbbit-peephole -mno-brcc @gol
-mcase-vector-pcrel -mcompact-casesi -mno-cond-exec -mearly-cbranchsi @gol
-mexpand-adddi -mindexed-loads -mlra -mlra-priority-none @gol
-mlra-priority-compact mlra-priority-noncompact -mno-millicode @gol
-mmixed-code -mq-class -mRcq -mRcw -msize-level=@var{level} @gol
-mtune=@var{cpu} -mmultcost=@var{num} -munalign-prob-threshold=@var{probability}}
@emph{ARM Options}
@gccoptlist{-mapcs-frame -mno-apcs-frame @gol
-mabi=@var{name} @gol
@ -11021,6 +11038,7 @@ platform.
@menu
* AArch64 Options::
* Adapteva Epiphany Options::
* ARC Options::
* ARM Options::
* AVR Options::
* Blackfin Options::
@ -11362,6 +11380,511 @@ purpose. The default is @option{-m1reg-none}.
@end table
@node ARC Options
@subsection ARC Options
@cindex ARC options
The following options control the architecture variant for which code
is being compiled:
@c architecture variants
@table @gcctabopt
@item -mbarrel-shifter
@opindex mbarrel-shifter
Generate instructions supported by barrel shifter. This is the default
unless @samp{-mcpu=ARC601} is in effect.
@item -mcpu=@var{cpu}
@opindex mcpu
Set architecture type, register usage, and instruction scheduling
parameters for @var{cpu}. There are also shortcut alias options
available for backward compatibility and convenience. Supported
values for @var{cpu} are
@table @samp
@opindex mA6
@opindex mARC600
@item ARC600
Compile for ARC600. Aliases: @option{-mA6}, @option{-mARC600}.
@item ARC601
@opindex mARC601
Compile for ARC601. Alias: @option{-mARC601}.
@item ARC700
@opindex mA7
@opindex mARC700
Compile for ARC700. Aliases: @option{-mA7}, @option{-mARC700}.
This is the default when configured with @samp{--with-cpu=arc700}@.
@end table
@item -mdpfp
@opindex mdpfp
@itemx -mdpfp-compact
@opindex mdpfp-compact
FPX: Generate Double Precision FPX instructions, tuned for the compact
implementation.
@item -mdpfp-fast
@opindex mdpfp-fast
FPX: Generate Double Precision FPX instructions, tuned for the fast
implementation.
@item -mno-dpfp-lrsr
@opindex mno-dpfp-lrsr
Disable LR and SR instructions from using FPX extension aux registers.
@item -mea
@opindex mea
Generate Extended arithmetic instructions. Currently only
@code{divaw}, @code{adds}, @code{subs}, and @code{sat16} are
supported. This is always enabled for @samp{-mcpu=ARC700}.
@item -mno-mpy
@opindex mno-mpy
Do not generate mpy instructions for ARC700.
@item -mmul32x16
@opindex mmul32x16
Generate 32x16 bit multiply and mac instructions.
@item -mmul64
@opindex mmul64
Generate mul64 and mulu64 instructions. Only valid for @samp{-mcpu=ARC600}.
@item -mnorm
@opindex mnorm
Generate norm instruction. This is the default if @samp{-mcpu=ARC700}
is in effect.
@item -mspfp
@opindex mspfp
@itemx -mspfp-compact
@opindex mspfp-compact
FPX: Generate Single Precision FPX instructions, tuned for the compact
implementation.
@item -mspfp-fast
@opindex mspfp-fast
FPX: Generate Single Precision FPX instructions, tuned for the fast
implementation.
@item -msimd
@opindex msimd
Enable generation of ARC SIMD instructions via target-specific
builtins. Only valid for @samp{-mcpu=ARC700}.
@item -msoft-float
@opindex msoft-float
This option ignored; it is provided for compatibility purposes only.
Software floating point code is emitted by default, and this default
can overridden by FPX options; @samp{mspfp}, @samp{mspfp-compact}, or
@samp{mspfp-fast} for single precision, and @samp{mdpfp},
@samp{mdpfp-compact}, or @samp{mdpfp-fast} for double precision.
@item -mswap
@opindex mswap
Generate swap instructions.
@end table
The following options are passed through to the assembler, and also
define preprocessor macro symbols.
@c Flags used by the assembler, but for which we define preprocessor
@c macro symbols as well.
@table @gcctabopt
@item -mdsp-packa
@opindex mdsp-packa
Passed down to the assembler to enable the DSP Pack A extensions.
Also sets the preprocessor symbol @code{__Xdsp_packa}.
@item -mdvbf
@opindex mdvbf
Passed down to the assembler to enable the dual viterbi butterfly
extension. Also sets the preprocessor symbol @code{__Xdvbf}.
@c ARC700 4.10 extension instruction
@item -mlock
@opindex mlock
Passed down to the assembler to enable the Locked Load/Store
Conditional extension. Also sets the preprocessor symbol
@code{__Xlock}.
@item -mmac-d16
@opindex mmac-d16
Passed down to the assembler. Also sets the preprocessor symbol
@code{__Xxmac_d16}.
@item -mmac-24
@opindex mmac-24
Passed down to the assembler. Also sets the preprocessor symbol
@code{__Xxmac_24}.
@c ARC700 4.10 extension instruction
@item -mrtsc
@opindex mrtsc
Passed down to the assembler to enable the 64-bit Time-Stamp Counter
extension instruction. Also sets the preprocessor symbol
@code{__Xrtsc}.
@c ARC700 4.10 extension instruction
@item -mswape
@opindex mswape
Passed down to the assembler to enable the swap byte ordering
extension instruction. Also sets the preprocessor symbol
@code{__Xswape}.
@item -mtelephony
@opindex mtelephony
Passed down to the assembler to enable dual and single operand
instructions for telephony. Also sets the preprocessor symbol
@code{__Xtelephony}.
@item -mxy
@opindex mxy
Passed down to the assembler to enable the XY Memory extension. Also
sets the preprocessor symbol @code{__Xxy}.
@end table
The following options control how the assembly code is annotated:
@c Assembly annotation options
@table @gcctabopt
@item -misize
@opindex misize
Annotate assembler instructions with estimated addresses.
@item -mannotate-align
@opindex mannotate-align
Explain what alignment considerations lead to the decision to make an
instruction short or long.
@end table
The following options are passed through to the linker:
@c options passed through to the linker
@table @gcctabopt
@item -marclinux
@opindex marclinux
Passed through to the linker, to specify use of the @code{arclinux} emulation.
This option is enabled by default in tool chains built for
@w{@code{arc-linux-uclibc}} and @w{@code{arceb-linux-uclibc}} targets
when profiling is not requested.
@item -marclinux_prof
@opindex marclinux_prof
Passed through to the linker, to specify use of the
@code{arclinux_prof} emulation. This option is enabled by default in
tool chains built for @w{@code{arc-linux-uclibc}} and
@w{@code{arceb-linux-uclibc}} targets when profiling is requested.
@end table
The following options control the semantics of generated code:
@c semantically relevant code generation options
@table @gcctabopt
@item -mepilogue-cfi
@opindex mepilogue-cfi
Enable generation of call frame information for epilogues.
@item -mno-epilogue-cfi
@opindex mno-epilogue-cfi
Disable generation of call frame information for epilogues.
@item -mlong-calls
@opindex mlong-calls
Generate call insns as register indirect calls, thus providing access
to the full 32-bit address range.
@item -mmedium-calls
@opindex mmedium-calls
Don't use less than 25 bit addressing range for calls, which is the
offset available for an unconditional branch-and-link
instruction. Conditional execution of function calls is suppressed, to
allow use of the 25-bit range, rather than the 21-bit range with
conditional branch-and-link. This is the default for tool chains built
for @w{@code{arc-linux-uclibc}} and @w{@code{arceb-linux-uclibc}} targets.
@item -mno-sdata
@opindex mno-sdata
Do not generate sdata references. This is the default for tool chains
built for @w{@code{arc-linux-uclibc}} and @w{@code{arceb-linux-uclibc}}
targets.
@item -mucb-mcount
@opindex mucb-mcount
Instrument with mcount calls as used in UCB code. I.e. do the
counting in the callee, not the caller. By default ARC instrumentation
counts in the caller.
@item -mvolatile-cache
@opindex mvolatile-cache
Use ordinarily cached memory accesses for volatile references. This is the
default.
@item -mno-volatile-cache
@opindex mno-volatile-cache
Enable cache bypass for volatile references.
@end table
The following options fine tune code generation:
@c code generation tuning options
@table @gcctabopt
@item -malign-call
@opindex malign-call
Do alignment optimizations for call instructions.
@item -mauto-modify-reg
@opindex mauto-modify-reg
Enable the use of pre/post modify with register displacement.
@item -mbbit-peephole
@opindex mbbit-peephole
Enable bbit peephole2.
@item -mno-brcc
@opindex mno-brcc
This option disables a target-specific pass in @file{arc_reorg} to
generate @code{BRcc} instructions. It has no effect on @code{BRcc}
generation driven by the combiner pass.
@item -mcase-vector-pcrel
@opindex mcase-vector-pcrel
Use pc-relative switch case tables - this enables case table shortening.
This is the default for @option{-Os}.
@item -mcompact-casesi
@opindex mcompact-casesi
Enable compact casesi pattern.
This is the default for @option{-Os}.
@item -mno-cond-exec
@opindex mno-cond-exec
Disable ARCompact specific pass to generate conditional execution instructions.
Due to delay slot scheduling and interactions between operand numbers,
literal sizes, instruction lengths, and the support for conditional execution,
the target-independent pass to generate conditional execution is often lacking,
so the ARC port has kept a special pass around that tries to find more
conditional execution generating opportunities after register allocation,
branch shortening, and delay slot scheduling have been done. This pass
generally, but not always, improves performance and code size, at the cost of
extra compilation time, which is why there is an option to switch it off.
If you have a problem with call instructions exceeding their allowable
offset range because they are conditionalized, you should consider using
@option{-mmedium-calls} instead.
@item -mearly-cbranchsi
@opindex mearly-cbranchsi
Enable pre-reload use of the cbranchsi pattern.
@item -mexpand-adddi
@opindex mexpand-adddi
Expand @code{adddi3} and @code{subdi3} at rtl generation time into
@code{add.f}, @code{adc} etc.
@item -mindexed-loads
@opindex mindexed-loads
Enable the use of indexed loads. This can be problematic because some
optimizers will then assume the that indexed stores exist, which is not
the case.
@item -mlra
@opindex mlra
Enable Local Register Allocation. This is still experimental for ARC,
so by default the compiler uses standard reload
(i.e. @samp{-mno-lra}).
@item -mlra-priority-none
@opindex mlra-priority-none
Don't indicate any priority for target registers.
@item -mlra-priority-compact
@opindex mlra-priority-compact
Indicate target register priority for r0..r3 / r12..r15.
@item -mlra-priority-noncompact
@opindex mlra-priority-noncompact
Reduce target regsiter priority for r0..r3 / r12..r15.
@item -mno-millicode
@opindex mno-millicode
When optimizing for size (using @option{-Os}), prologues and epilogues
that have to save or restore a large number of registers are often
shortened by using call to a special function in libgcc; this is
referred to as a @emph{millicode} call. As these calls can pose
performance issues, and/or cause linking issues when linking in a
nonstandard way, this option is provided to turn off millicode call
generation.
@item -mmixed-code
@opindex mmixed-code
Tweak register allocation to help 16-bit instruction generation.
This generally has the effect of decreasing the average instruction size
while increasing the instruction count.
@item -mq-class
@opindex mq-class
Enable 'q' instruction alternatives.
This is the default for @option{-Os}.
@item -mRcq
@opindex mRcq
Enable Rcq constraint handling - most short code generation depends on this.
This is the default.
@item -mRcw
@opindex mRcw
Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
This is the default.
@item -msize-level=@var{level}
@ opindex msize-level
Fine-tune size optimization with regards to instruction lengths and alignment.
The recognized values for @var{level} are:
@table @samp
@item 0
No size optimization. This level is deprecated and treated like @samp{1}.
@item 1
Short instructions are used opportunistically.
@item 2
In addition, alignment of loops and of code after barriers are dropped.
@item 3
In addition, optional data alignment is dropped, and the option @option{Os} is enabled.
@end table
This defaults to @samp{3} when @option{-Os} is in effect. Otherwise,
the behavior when this is not set is equivalent to level @samp{1}.
@item -mtune=@var{cpu}
@opindex mtune
Set instruction scheduling parameters for @var{cpu}, overriding any implied
by @option{-mcpu=}.
Supported values for @var{cpu} are
@table @samp
@item ARC600
Tune for ARC600 cpu.
@item ARC601
Tune for ARC601 cpu.
@item ARC700
Tune for ARC700 cpu with standard multiplier block.
@item ARC700-xmac
Tune for ARC700 cpu with XMAC block.
@item ARC725D
Tune for ARC725D cpu.
@item ARC750D
Tune for ARC750D cpu.
@end table
@item -mmultcost=@var{num}
@opindex mmultcost
Cost to assume for a multiply instruction, with @samp{4} being equal to a
normal instruction.
@item -munalign-prob-threshold=@var{probability}
@opindex munalign-prob-threshold
Set probability threshold for unaligning branches.
When tuning for @samp{ARC700} and optimizing for speed, branches without
filled delay slot are preferably emitted unaligned and long, unless
profiling indicates that the probability for the branch to be taken
is below @var{probability}. @xref{Cross-profiling}.
The default is (REG_BR_PROB_BASE/2), i.e.@: 5000.
@end table
The following options are maintained for backward compatibility, but
are now deprecated and will be removed in a future release:
@c Deprecated options
@table @gcctabopt
@item -margonaut
@opindex margonaut
Obsolete FPX.
@item -mbig-endian
@opindex mbig-endian
@itemx -EB
@opindex EB
Compile code for big endian targets. Use of these options is now
deprecated. Users wanting big-endian code, should use the
@w{@code{arceb-elf32}} and @w{@code{arceb-linux-uclibc}} targets when
building the tool chain, for which big-endian is the default.
@item -mlittle-endian
@opindex mlittle-endian
@itemx -EL
@opindex EL
Compile code for little endian targets. Use of these options is now
deprecated. Users wanting little-endian code should use the
@w{@code{arc-elf32}} and @w{@code{arc-linux-uclibc}} targets when
building the tool chain, for which little-endian is the default.
@item -mbarrel_shifter
@opindex mbarrel_shifter
Replaced by @samp{-mbarrel-shifter}
@item -mdpfp_compact
@opindex mdpfp_compact
Replaced by @samp{-mdpfp-compact}
@item -mdpfp_fast
@opindex mdpfp_fast
Replaced by @samp{-mdpfp-fast}
@item -mdsp_packa
@opindex mdsp_packa
Replaced by @samp{-mdsp-packa}
@item -mEA
@opindex mEA
Replaced by @samp{-mea}
@item -mmac_24
@opindex mmac_24
Replaced by @samp{-mmac-24}
@item -mmac_d16
@opindex mmac_d16
Replaced by @samp{-mmac-d16}
@item -mspfp_compact
@opindex mspfp_compact
Replaced by @samp{-mspfp-compact}
@item -mspfp_fast
@opindex mspfp_fast
Replaced by @samp{-mspfp-fast}
@item -mtune=@var{cpu}
@opindex mtune
Values @samp{arc600}, @samp{arc601}, @samp{arc700} and
@samp{arc700-xmac} for @var{cpu} are replaced by @samp{ARC600},
@samp{ARC601}, @samp{ARC700} and @samp{ARC700-xmac} respectively
@item -multcost=@var{num}
@opindex multcost
Replaced by @samp{-mmultcost}.
@end table
@node ARM Options
@subsection ARM Options
@cindex ARM options

48
gcc/doc/md.texi
View File

@ -1725,6 +1725,54 @@ DF modes
@end table
@item ARC ---@file{config/arc/constraints.md}
@table @code
@item q
Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
@code{r12}-@code{r15}. This constraint can only match when the @option{-mq}
option is in effect.
@item e
Registers usable as base-regs of memory addresses in ARCompact 16-bit memory
instructions: @code{r0}-@code{r3}, @code{r12}-@code{r15}, @code{sp}.
This constraint can only match when the @option{-mq}
option is in effect.
@item D
ARC FPX (dpfp) 64-bit registers. @code{D0}, @code{D1}.
@item I
A signed 12-bit integer constant.
@item Cal
constant for arithmetic/logical operations. This might be any constant
that can be put into a long immediate by the assmbler or linker without
involving a PIC relocation.
@item K
A 3-bit unsigned integer constant.
@item L
A 6-bit unsigned integer constant.
@item CnL
One's complement of a 6-bit unsigned integer constant.
@item CmL
Two's complement of a 6-bit unsigned integer constant.
@item M
A 5-bit unsigned integer constant.
@item O
A 7-bit unsigned integer constant.
@item P
A 8-bit unsigned integer constant.
@item H
Any const_double value.
@end table
@item ARM family---@file{config/arm/constraints.md}
@table @code
@item w