sparc.c (arith_4096_operand, [...]): New predicates.
* config/sparc/sparc.c (arith_4096_operand, arith_add_operand, arith_double_4096_operand, arith_double_add_operand): New predicates. * config/sparc/sparc.h (PREDICATE_CODES): Add them, declare them. * config/sparc/sparc.md (adddi3, addsi3, subdi3, subsi3): Use them to transform add/sub 4096 into add/sub -4096. From-SVN: r21961
This commit is contained in:
Jakub Jelinek
David S. Miller
parent
00045f5275
commit
5d6d333901
@ -1,3 +1,12 @@
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Tue Aug 25 05:48:18 1998 Jakub Jelinek <jj@sunsite.ms.mff.cuni.cz>
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* config/sparc/sparc.c (arith_4096_operand, arith_add_operand,
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arith_double_4096_operand, arith_double_add_operand): New
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predicates.
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* config/sparc/sparc.h (PREDICATE_CODES): Add them, declare them.
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* config/sparc/sparc.md (adddi3, addsi3, subdi3, subsi3): Use
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them to transform add/sub 4096 into add/sub -4096.
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Mon Aug 24 23:31:03 1998 David S. Miller <davem@pierdol.cobaltmicro.com>
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* loop.c (scan_loop): Allocate some slop to handle pseudos
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@ -780,6 +780,30 @@ arith_operand (op, mode)
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return SPARC_SIMM13_P (val);
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}
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/* Return true if OP is a constant 4096 */
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int
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arith_4096_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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int val;
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if (GET_CODE (op) != CONST_INT)
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return 0;
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val = INTVAL (op) & 0xffffffff;
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return val == 4096;
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}
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/* Return true if OP is suitable as second operand for add/sub */
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int
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arith_add_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return arith_operand (op, mode) || arith_4096_operand (op, mode);
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}
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/* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
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immediate field of OR and XOR instructions. Used for 64-bit
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constant formation patterns. */
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@ -879,6 +903,30 @@ arith_double_operand (op, mode)
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&& (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
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}
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/* Return true if OP is a constant 4096 for DImode on ARCH64 */
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int
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arith_double_4096_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return (TARGET_ARCH64 &&
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((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
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(GET_CODE (op) == CONST_DOUBLE &&
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CONST_DOUBLE_LOW (op) == 4096 &&
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CONST_DOUBLE_HIGH (op) == 0)));
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}
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/* Return true if OP is suitable as second operand for add/sub in DImode */
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int
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arith_double_add_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
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}
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/* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
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can fit in an 11 bit immediate field. This is an acceptable DImode
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operand for the movcc instructions. */
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@ -3214,9 +3214,11 @@ do { \
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{"cc_arithop", {AND, IOR, XOR}}, \
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{"cc_arithopn", {AND, IOR}}, \
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{"arith_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT}}, \
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{"arith_add_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT}}, \
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{"arith11_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT}}, \
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{"arith10_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT}}, \
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{"arith_double_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, CONST_DOUBLE}}, \
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{"arith_double_add_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, CONST_DOUBLE}},\
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{"arith11_double_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, CONST_DOUBLE}}, \
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{"arith10_double_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, CONST_DOUBLE}}, \
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{"small_int", {CONST_INT, CONSTANT_P_RTX}}, \
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@ -3262,7 +3264,11 @@ extern int arith10_operand ();
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extern int arith11_double_operand ();
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extern int arith11_operand ();
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extern int arith_double_operand ();
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extern int arith_double_4096_operand ();
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extern int arith_double_add_operand ();
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extern int arith_operand ();
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extern int arith_4096_operand ();
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extern int arith_add_operand ();
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extern int call_operand_address ();
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extern int input_operand ();
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extern int zero_operand ();
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@ -4534,7 +4534,7 @@
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(define_expand "adddi3"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
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(match_operand:DI 2 "arith_double_operand" "rHI")))]
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(match_operand:DI 2 "arith_double_add_operand" "rHI")))]
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""
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"
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{
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@ -4548,6 +4548,13 @@
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gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
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DONE;
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}
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if (arith_double_4096_operand(operands[2], DImode))
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{
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emit_insn (gen_rtx_SET (VOIDmode, operands[0],
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gen_rtx_MINUS (DImode, operands[1],
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GEN_INT(-4096))));
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DONE;
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}
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}")
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(define_insn "adddi3_insn_sp32"
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@ -4749,7 +4756,23 @@
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[(set_attr "type" "binary")
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(set_attr "length" "1")])
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(define_insn "addsi3"
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(define_expand "addsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,d")
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(plus:SI (match_operand:SI 1 "arith_operand" "%r,d")
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(match_operand:SI 2 "arith_add_operand" "rI,d")))]
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""
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"
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{
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if (arith_4096_operand(operands[2], DImode))
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{
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emit_insn (gen_rtx_SET (VOIDmode, operands[0],
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gen_rtx_MINUS (SImode, operands[1],
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GEN_INT(-4096))));
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DONE;
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}
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}")
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(define_insn "*addsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,d")
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(plus:SI (match_operand:SI 1 "arith_operand" "%r,d")
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(match_operand:SI 2 "arith_operand" "rI,d")))]
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@ -4807,7 +4830,7 @@
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(define_expand "subdi3"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(minus:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:DI 2 "arith_double_operand" "rHI")))]
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(match_operand:DI 2 "arith_double_add_operand" "rHI")))]
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""
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"
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{
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@ -4821,6 +4844,13 @@
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gen_rtx_REG (CCmode, SPARC_ICC_REG)))));
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DONE;
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}
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if (arith_double_4096_operand(operands[2], DImode))
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{
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emit_insn (gen_rtx_SET (VOIDmode, operands[0],
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gen_rtx_PLUS (DImode, operands[1],
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GEN_INT(-4096))));
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DONE;
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}
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}")
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(define_insn "*subdi3_sp32"
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@ -4925,7 +4955,23 @@
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[(set_attr "type" "binary")
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(set_attr "length" "1")])
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(define_insn "subsi3"
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(define_expand "subsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,d")
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(minus:SI (match_operand:SI 1 "register_operand" "r,d")
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(match_operand:SI 2 "arith_add_operand" "rI,d")))]
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""
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"
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{
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if (arith_4096_operand(operands[2], DImode))
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{
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emit_insn (gen_rtx_SET (VOIDmode, operands[0],
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gen_rtx_PLUS (SImode, operands[1],
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GEN_INT(-4096))));
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DONE;
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}
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}")
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(define_insn "*subsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,d")
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(minus:SI (match_operand:SI 1 "register_operand" "r,d")
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(match_operand:SI 2 "arith_operand" "rI,d")))]
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