re PR target/50446 ([avr] Implement rotate patterns with offset 1)
PR target/50446 * config/avr/avr.md (rotlqi3): Support all offsets 0..7. (rotlqi3_4): Turn insn into expander. (*rotlqi3): New insn. (rotlhi3, rotlsi3): Support rotate left/right by 1. (*rotlhi2.1, *rotlhi2.15): New insns. (*rotlsi2.1, *rotlsi2.31): New insns. * config/avr/constraints.md (C03, C05, C06, C07): New constraints. From-SVN: r179116
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Georg-Johann Lay
Georg-Johann Lay
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9acebb8a99
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5d94b98863
@ -1,3 +1,14 @@
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2011-09-23 Georg-Johann Lay <avr@gjlay.de>
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PR target/50446
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* config/avr/avr.md (rotlqi3): Support all offsets 0..7.
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(rotlqi3_4): Turn insn into expander.
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(*rotlqi3): New insn.
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(rotlhi3, rotlsi3): Support rotate left/right by 1.
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(*rotlhi2.1, *rotlhi2.15): New insns.
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(*rotlsi2.1, *rotlsi2.31): New insns.
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* config/avr/constraints.md (C03, C05, C06, C07): New constraints.
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2011-09-23 Bin Cheng <bin.cheng@arm.com>
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* config/arm/bpabi.h (BE8_LINK_SPEC): Add cortex-m arch
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@ -2391,22 +2391,37 @@
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(define_expand "rotlqi3"
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[(set (match_operand:QI 0 "register_operand" "")
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(rotate:QI (match_operand:QI 1 "register_operand" "")
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(match_operand:QI 2 "const_int_operand" "")))]
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(match_operand:QI 2 "const_0_to_7_operand" "")))]
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""
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"
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{
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if (!CONST_INT_P (operands[2]) || (INTVAL (operands[2]) != 4))
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{
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if (!CONST_INT_P (operands[2]))
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FAIL;
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}")
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(define_insn "rotlqi3_4"
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[(set (match_operand:QI 0 "register_operand" "=r")
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(rotate:QI (match_operand:QI 1 "register_operand" "0")
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(const_int 4)))]
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operands[2] = gen_int_mode (INTVAL (operands[2]) & 7, QImode);
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})
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;; Expander used by __builtin_avr_swap
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(define_expand "rotlqi3_4"
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[(set (match_operand:QI 0 "register_operand" "")
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(rotate:QI (match_operand:QI 1 "register_operand" "")
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(const_int 4)))])
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(define_insn "*rotlqi3"
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[(set (match_operand:QI 0 "register_operand" "=r,r,r ,r ,r ,r ,r ,r")
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(rotate:QI (match_operand:QI 1 "register_operand" "0,0,0 ,0 ,0 ,0 ,0 ,0")
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(match_operand:QI 2 "const_0_to_7_operand" "P,K,C03,C04,C05,C06,C07,L")))]
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""
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"swap %0"
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[(set_attr "length" "1")
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(set_attr "cc" "none")])
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"@
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lsl %0\;adc %0,__zero_reg__
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lsl %0\;adc %0,__zero_reg__\;lsl %0\;adc %0,__zero_reg__
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swap %0\;bst %0,0\;ror %0\;bld %0,7
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swap %0
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swap %0\;lsl %0\;adc %0,__zero_reg__
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swap %0\;lsl %0\;adc %0,__zero_reg__\;lsl %0\;adc %0,__zero_reg__
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bst %0,0\;ror %0\;bld %0,7
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"
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[(set_attr "length" "2,4,4,1,3,5,3,0")
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(set_attr "cc" "set_n,set_n,clobber,none,set_n,set_n,clobber,none")])
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;; Split all rotates of HI,SI and DImode registers where rotation is by
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;; a whole number of bytes. The split creates the appropriate moves and
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@ -2418,6 +2433,9 @@
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(define_mode_attr rotx [(DI "&r,&r,X") (SI "&r,&r,X") (HI "X,X,X")])
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(define_mode_attr rotsmode [(DI "QI") (SI "HI") (HI "QI")])
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;; "rotlhi3"
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;; "rotlsi3"
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;; "rotldi3"
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(define_expand "rotl<mode>3"
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[(parallel [(set (match_operand:HIDI 0 "register_operand" "")
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(rotate:HIDI (match_operand:HIDI 1 "register_operand" "")
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@ -2425,18 +2443,69 @@
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(clobber (match_dup 3))])]
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""
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{
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if (CONST_INT_P (operands[2])
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&& 0 == INTVAL (operands[2]) % 8)
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int offset;
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if (!CONST_INT_P (operands[2]))
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FAIL;
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offset = INTVAL (operands[2]);
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if (0 == offset % 8)
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{
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if (AVR_HAVE_MOVW && 0 == INTVAL (operands[2]) % 16)
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if (AVR_HAVE_MOVW && 0 == offset % 16)
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operands[3] = gen_rtx_SCRATCH (<rotsmode>mode);
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else
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operands[3] = gen_rtx_SCRATCH (QImode);
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}
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else if (<MODE>mode != DImode
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&& (offset == 1
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|| offset == GET_MODE_BITSIZE (<MODE>mode) -1))
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{
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/*; Support rotate left/right by 1 */
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emit_move_insn (operands[0],
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gen_rtx_ROTATE (<MODE>mode, operands[1], operands[2]));
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DONE;
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}
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else
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FAIL;
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})
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(define_insn "*rotlhi2.1"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(rotate:HI (match_operand:HI 1 "register_operand" "0")
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(const_int 1)))]
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""
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"lsl %A0\;rol %B0\;adc %A0,__zero_reg__"
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[(set_attr "length" "3")
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(set_attr "cc" "clobber")])
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(define_insn "*rotlhi2.15"
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[(set (match_operand:HI 0 "register_operand" "=r")
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(rotate:HI (match_operand:HI 1 "register_operand" "0")
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(const_int 15)))]
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""
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"bst %A0,0\;ror %B0\;ror %A0\;bld %B0,7"
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[(set_attr "length" "3")
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(set_attr "cc" "clobber")])
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(define_insn "*rotlsi2.1"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(rotate:SI (match_operand:SI 1 "register_operand" "0")
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(const_int 1)))]
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""
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"lsl %A0\;rol %B0\;rol %C0\;rol %D0\;adc %A0,__zero_reg__"
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[(set_attr "length" "5")
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(set_attr "cc" "clobber")])
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(define_insn "*rotlsi2.31"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(rotate:SI (match_operand:SI 1 "register_operand" "0")
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(const_int 31)))]
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""
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"bst %A0,0\;ror %D0\;ror %C0\;ror %B0\;ror %A0\;bld %D0,7"
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[(set_attr "length" "6")
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(set_attr "cc" "clobber")])
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;; Overlapping non-HImode registers often (but not always) need a scratch.
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;; The best we can do is use early clobber alternative "#&r" so that
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@ -2444,7 +2513,11 @@
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;; allocation does not prefer non-overlapping.
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; Split word aligned rotates using scratch that is mode dependent.
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;; Split word aligned rotates using scratch that is mode dependent.
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;; "*rotwhi"
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;; "*rotwsi"
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;; "*rotwdi"
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(define_insn_and_split "*rotw<mode>"
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[(set (match_operand:HIDI 0 "register_operand" "=r,r,#&r")
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(rotate:HIDI (match_operand:HIDI 1 "register_operand" "0,r,r")
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@ -2462,7 +2535,11 @@
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})
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; Split byte aligned rotates using scratch that is always QI mode.
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;; Split byte aligned rotates using scratch that is always QI mode.
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;; "*rotbhi"
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;; "*rotbsi"
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;; "*rotbdi"
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(define_insn_and_split "*rotb<mode>"
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[(set (match_operand:HIDI 0 "register_operand" "=r,r,#&r")
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(rotate:HIDI (match_operand:HIDI 1 "register_operand" "0,r,r")
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@ -108,11 +108,31 @@
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(and (match_code "mem")
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(match_test "extra_constraint_Q (op)")))
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(define_constraint "C03"
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"Constant integer 3."
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(and (match_code "const_int")
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(match_test "ival == 3")))
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(define_constraint "C04"
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"Constant integer 4."
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(and (match_code "const_int")
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(match_test "ival == 4")))
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(define_constraint "C05"
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"Constant integer 5."
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(and (match_code "const_int")
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(match_test "ival == 5")))
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(define_constraint "C06"
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"Constant integer 6."
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(and (match_code "const_int")
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(match_test "ival == 6")))
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(define_constraint "C07"
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"Constant integer 7."
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(and (match_code "const_int")
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(match_test "ival == 7")))
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(define_constraint "Ca2"
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"Constant 2-byte integer that allows AND without clobber register."
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(and (match_code "const_int")
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