predicates.md (logical_and_operand): New predicate.
* config/sh/predicates.md (logical_and_operand): New predicate. * config/sh/constraints.md (Jmb, Jmw): New constraints. * config/sh/sh.md (andsi3): Move expander above insns. Add handling of 0xFFFF constant. Use logical_and_operand predicate and satisfies_constraint_Jmb, satisfies_constraint_Jmw. (*andsi3_compact): Make it an insn_and_split. Use logical_and_operand predicate. Add Jmb,Jmw alternatives. From-SVN: r189241
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Oleg Endo
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c128d2031e
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@ -1,3 +1,13 @@
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2012-07-03 Oleg Endo <olegendo@gcc.gnu.org>
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* config/sh/predicates.md (logical_and_operand): New predicate.
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* config/sh/constraints.md (Jmb, Jmw): New constraints.
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* config/sh/sh.md (andsi3): Move expander above insns. Add handling
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of 0xFFFF constant. Use logical_and_operand predicate and
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satisfies_constraint_Jmb, satisfies_constraint_Jmw.
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(*andsi3_compact): Make it an insn_and_split. Use
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logical_and_operand predicate. Add Jmb,Jmw alternatives.
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2012-07-03 Jason Merrill <jason@redhat.com>
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PR c++/53826
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@ -31,6 +31,8 @@
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;; IJKLMNOP: CONT_INT constants
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;; Ixx: signed xx bit
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;; J16: 0xffffffff00000000 | 0x00000000ffffffff
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;; Jmb: 0x000000FF
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;; Jmw: 0x0000FFFF
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;; Kxx: unsigned xx bit
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;; M: 1
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;; N: 0
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@ -135,6 +137,16 @@
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(and (match_code "const_int")
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(match_test "CONST_OK_FOR_J16 (ival)")))
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(define_constraint "Jmb"
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"Low byte mask constant 0x000000FF"
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(and (match_code "const_int")
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(match_test "ival == 0xFF")))
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(define_constraint "Jmw"
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"Low word mask constant 0x0000FFFF"
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(and (match_code "const_int")
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(match_test "ival == 0xFFFF")))
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(define_constraint "K03"
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"An unsigned 3-bit constant, as used in SH2A bclr, bset, etc."
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(and (match_code "const_int")
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@ -574,6 +574,21 @@
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return 0;
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})
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;; Like logical_operand but allows additional constant values which can be
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;; done with zero extensions. Used for the second operand of and insns.
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(define_predicate "logical_and_operand"
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(match_code "subreg,reg,const_int")
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{
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if (logical_operand (op, mode))
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return 1;
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if (! TARGET_SHMEDIA
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&& (satisfies_constraint_Jmb (op) || satisfies_constraint_Jmw (op)))
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return 1;
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return 0;
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})
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;; TODO: Add a comment here.
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(define_predicate "logical_operator"
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@ -3113,12 +3113,55 @@ label:
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;; Logical operations
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;; -------------------------------------------------------------------------
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(define_insn "*andsi3_compact"
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[(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
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(and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
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(match_operand:SI 2 "logical_operand" "K08,r")))]
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(define_expand "andsi3"
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[(set (match_operand:SI 0 "arith_reg_operand" "")
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(and:SI (match_operand:SI 1 "logical_reg_operand" "")
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(match_operand:SI 2 "logical_and_operand" "")))]
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""
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{
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/* If it is possible to turn the and insn into a zero extension
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already, redundant zero extensions will be folded, which results
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in better code.
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Ideally the splitter of *andsi_compact would be enough, if reundant
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zero extensions were detected after the combine pass, which does not
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happen at the moment. */
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if (TARGET_SH1)
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{
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if (satisfies_constraint_Jmb (operands[2]))
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{
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emit_insn (gen_zero_extendqisi2 (operands[0],
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gen_lowpart (QImode, operands[1])));
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DONE;
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}
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else if (satisfies_constraint_Jmw (operands[2]))
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{
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emit_insn (gen_zero_extendhisi2 (operands[0],
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gen_lowpart (HImode, operands[1])));
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DONE;
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}
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}
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})
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(define_insn_and_split "*andsi_compact"
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[(set (match_operand:SI 0 "arith_reg_dest" "=r,r,z,r")
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(and:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,0,0")
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(match_operand:SI 2 "logical_and_operand" "Jmb,Jmw,K08,r")))]
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"TARGET_SH1"
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"and %2,%0"
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"@
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extu.b %1,%0
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extu.w %1,%0
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and %2,%0
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and %2,%0"
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"&& 1"
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[(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
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{
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if (satisfies_constraint_Jmb (operands[2]))
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operands[1] = gen_lowpart (QImode, operands[1]);
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else if (satisfies_constraint_Jmw (operands[2]))
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operands[1] = gen_lowpart (HImode, operands[1]);
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else
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FAIL;
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}
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[(set_attr "type" "arith")])
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(define_insn "*andsi3_media"
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@ -3139,24 +3182,6 @@ label:
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"bclr\\t%W2,%0"
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[(set_attr "type" "arith")])
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;; If the constant is 255, then emit an extu.b instruction instead of an
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;; and, since that will give better code.
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(define_expand "andsi3"
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[(set (match_operand:SI 0 "arith_reg_operand" "")
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(and:SI (match_operand:SI 1 "logical_reg_operand" "")
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(match_operand:SI 2 "logical_operand" "")))]
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""
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{
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if (TARGET_SH1
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&& CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 255)
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{
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emit_insn (gen_zero_extendqisi2 (operands[0],
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gen_lowpart (QImode, operands[1])));
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DONE;
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}
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})
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(define_insn_and_split "anddi3"
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[(set (match_operand:DI 0 "arith_reg_dest" "=r,r,r")
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(and:DI (match_operand:DI 1 "arith_reg_operand" "%r,r,r")
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