c4x.c: Include system.h.
* config/c4x/c4x.c: Include system.h. (c4x_caller_save_map): Disable caller save for RC. (c4x_optimization_options): Disable scheduling before reload. (valid_parallel_load_store) : Define return type as int. Remove unused variable regs. * config/c4x/c4x.h (REGISTER_MOVE_COST): Make independent of register class. * config/c4x/c4x.md (rotlqi3, rotrqi3): Fix up emitted RTL to handle rotations. (*db, decrement_and_branch_until_zero): Fix up constraints to keep reload happy. From-SVN: r24600
This commit is contained in:
Michael Hayes
Michael Hayes
parent
dfa27ef1db
commit
5e6a42d9e4
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@ -1,3 +1,17 @@
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Sun Jan 10 15:35:41 1999 Michael Hayes <m.hayes@elec.canterbury.ac.nz>
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* config/c4x/c4x.c: Include system.h.
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(c4x_caller_save_map): Disable caller save for RC.
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(c4x_optimization_options): Disable scheduling before reload.
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(valid_parallel_load_store) : Define return type as int.
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Remove unused variable regs.
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* config/c4x/c4x.h (REGISTER_MOVE_COST): Make independent of register
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class.
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* config/c4x/c4x.md (rotlqi3, rotrqi3): Fix up emitted RTL to
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handle rotations.
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(*db, decrement_and_branch_until_zero): Fix up constraints
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to keep reload happy.
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Sat Jan 9 18:35:29 1999 Richard Henderson <rth@cygnus.com>
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* tree.c (make_node): Call bzero instead of inline clear.
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@ -1,5 +1,5 @@
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/* Subroutines for assembler code output on the TMS320C[34]x
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Copyright (C) 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
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Copyright (C) 1994-98, 1999 Free Software Foundation, Inc.
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Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
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and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
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@ -22,10 +22,8 @@
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Boston, MA 02111-1307, USA. */
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/* Some output-actions in c4x.md need these. */
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdarg.h>
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#include "config.h"
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#include "system.h"
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#include "toplev.h"
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#include "rtl.h"
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#include "regs.h"
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@ -121,7 +119,7 @@ enum machine_mode c4x_caller_save_map[FIRST_PSEUDO_REGISTER] =
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VOIDmode, /* IIF/IOF No */
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QImode, /* RS QI No */
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QImode, /* RE QI No */
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QImode, /* RC QI No */
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VOIDmode, /* RC QI No */
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QFmode, /* R8 QI, QF, HF QI */
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HFmode, /* R9 QI, QF, HF No */
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HFmode, /* R10 QI, QF, HF No */
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@ -202,11 +200,6 @@ c4x_override_options ()
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/* Convert foo / 8.0 into foo * 0.125, etc. */
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flag_fast_math = 1;
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/* We should phase out the following at some stage.
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This provides compatibility with the old -mno-rptb option. */
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if (! TARGET_RPTB && flag_branch_on_count_reg)
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flag_branch_on_count_reg = 0;
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/* We should phase out the following at some stage.
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This provides compatibility with the old -mno-aliases option. */
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if (! TARGET_ALIASES && ! flag_argument_noalias)
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@ -219,6 +212,12 @@ c4x_optimization_options (level, size)
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int level;
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int size ATTRIBUTE_UNUSED;
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{
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/* Scheduling before register allocation can screw up global
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register allocation, especially for functions that use MPY||ADD
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instructions. The benefit we gain we get by scheduling before
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register allocation is probably marginal anyhow. */
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flag_schedule_insns = 0;
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/* When optimizing, enable use of RPTB instruction. */
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if (level >= 1)
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flag_branch_on_count_reg = 1;
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@ -3194,6 +3193,7 @@ c4x_label_conflict (insn, jump, db)
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/* Validate combination of operands for parallel load/store instructions. */
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int
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valid_parallel_load_store (operands, mode)
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rtx *operands;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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@ -3254,7 +3254,6 @@ valid_parallel_operands_4 (operands, mode)
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rtx *operands;
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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int regs = 0;
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rtx op0 = operands[0];
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rtx op2 = operands[2];
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@ -1,5 +1,5 @@
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/* Definitions of target machine for GNU compiler. TMS320C[34]x
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Copyright (C) 1994, 1995, 1996, 1997 Free Software Foundation, Inc.
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Copyright (C) 1994-98, 1999 Free Software Foundation, Inc.
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Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
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and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
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@ -1713,11 +1713,10 @@ if (REG_P (OP1) && ! REG_P (OP0)) \
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#define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
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|| INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
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/* Make the Rx register a little easier to use so they are used for
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calculations and the ARx registers are used for addressing. */
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/* Compute extra cost of moving data between one register class
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and another. */
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#define REGISTER_MOVE_COST(FROM, TO) \
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(EXPENSIVE_CLASS_P(TO) ? 5 : EXPENSIVE_CLASS_P(FROM) ? 4 : 3)
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#define REGISTER_MOVE_COST(FROM, TO) 2
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/* Memory move cost is same as fast register move. Maybe this should
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be bumped up? */
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@ -1,7 +1,7 @@
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;; Machine description for the TMS320C[34]x for GNU C compiler
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;; Copyright (C) 1994, 95-98, 1999 Free Software Foundation, Inc.
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;; Copyright (C) 1994-98, 1999 Free Software Foundation, Inc.
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;; Contributed by Michael Hayes (m.hayes@elec.canterbury.cri.nz)
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;; Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
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;; and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl)
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;; This file is part of GNU CC.
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@ -369,7 +369,7 @@
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(define_attr "in_annul_slot_3" "false,true"
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(if_then_else (and (eq_attr "cpu" "c4x")
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(eq_attr "type" "!jump,call,rets,jmpc,db,dbc,repeat,repeat_top,laj,push,pop,multi"))
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(eq_attr "type" "!jump,call,rets,jmpc,unarycc,binarycc,db,dbc,repeat,repeat_top,laj,push,pop,multi"))
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(const_string "true")
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(const_string "false")))
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@ -1458,19 +1458,26 @@
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(match_operand:QI 2 "const_int_operand" "")))
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(clobber (reg:CC 21))])]
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""
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"if (INTVAL (operands[2]) >= 4)
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"if (INTVAL (operands[2]) > 4)
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FAIL; /* Open code as two shifts and an or */
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if (INTVAL (operands[2]) > 1)
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{
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int i;
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rtx tmp;
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/* If we have 4 or fewer shifts, then it is probably faster
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to emit separate ROL instructions. A C3x requires
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at least 4 instructions (a C4x requires at least 3), to
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perform a rotation by shifts. */
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for (i = 0; i < INTVAL (operands[2]); i++)
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emit_insn (gen_rotl_1_clobber (operands[0], operands[1]));
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tmp = operands[1];
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for (i = 0; i < INTVAL (operands[2]) - 1; i++)
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{
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tmp = gen_reg_rtx (QImode);
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emit_insn (gen_rotl_1_clobber (tmp, operands[1]));
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operands[1] = tmp;
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}
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emit_insn (gen_rotl_1_clobber (operands[0], tmp));
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DONE;
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}")
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@ -1493,19 +1500,26 @@
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(match_operand:QI 2 "const_int_operand" "")))
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(clobber (reg:CC 21))])]
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""
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"if (INTVAL (operands[2]) >= 4)
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"if (INTVAL (operands[2]) > 4)
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FAIL; /* Open code as two shifts and an or */
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if (INTVAL (operands[2]) > 1)
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{
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int i;
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rtx tmp;
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/* If we have 4 or fewer shifts, then it is probably faster
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to emit separate ROL instructions. A C3x requires
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at least 4 instructions (a C4x requires at least 3), to
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perform a rotation by shifts. */
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for (i = 0; i < INTVAL (operands[2]); i++)
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emit_insn (gen_rotr_1_clobber (operands[0], operands[1]));
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tmp = operands[1];
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for (i = 0; i < INTVAL (operands[2]) - 1; i++)
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{
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tmp = gen_reg_rtx (QImode);
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emit_insn (gen_rotr_1_clobber (tmp, operands[1]));
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operands[1] = tmp;
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}
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emit_insn (gen_rotr_1_clobber (operands[0], tmp));
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DONE;
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}")
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@ -4484,11 +4498,11 @@
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; have an option to disable this instruction.
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(define_insn "*db"
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[(set (pc)
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(if_then_else (ne (match_operand:QI 2 "addr_reg_operand" "0,0,0,0")
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(if_then_else (ne (match_operand:QI 0 "addr_reg_operand" "+a,?*d,??*r,!m")
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(const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))
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(set (match_operand:QI 0 "addr_reg_operand" "+a,?*d,??*r,!m")
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(set (match_dup 0)
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(plus:QI (match_dup 0)
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(const_int -1)))
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(clobber (reg:CC_NOOV 21))]
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@ -4505,14 +4519,26 @@
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"
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[(set_attr "type" "db,jmpc,jmpc,jmpc")])
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; This insn is used for some loop tests, typically loops reversed when
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; strength reduction is used. It is actually created when the instruction
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; combination phase combines the special loop test. Since this insn
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; is both a jump insn and has an output, it must deal with its own
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; reloads, hence the `m' constraints.
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; The C4x does the decrement and then compares the result against zero.
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; It branches if the result was greater than or equal to zero.
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; In the RTL the comparison and decrement are assumed to happen
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; at the same time so we bias the iteration counter with by -1
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; when we make the test.
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(define_insn "decrement_and_branch_until_zero"
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[(set (pc)
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(if_then_else (ge (plus:QI (match_operand:QI 2 "addr_reg_operand" "0,0,0,0")
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(if_then_else (ge (plus:QI (match_operand:QI 0 "addr_reg_operand" "+a,?*d,??*r,!m")
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(const_int -1))
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(const_int 0))
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(label_ref (match_operand 1 "" ""))
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(pc)))
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(set (match_operand:QI 0 "addr_reg_operand" "+a,?*d,??*r,!m")
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(set (match_dup 0)
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(plus:QI (match_dup 0)
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(const_int -1)))
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(clobber (reg:CC_NOOV 21))]
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