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arm.md (split for eq(reg, 0)): Add variants for ARMv5 and Thumb2. 

(peepholes for eq(reg, not-0)): Ensure condition register is dead after
	pattern.  Use more efficient sequences on ARMv5 and Thumb2.

From-SVN: r200197
This commit is contained in:
Richard Earnshaw 2013-06-19 12:25:26 +00:00 committed by Richard Earnshaw
parent 5fdc1e5d8a
commit 5e7f6aaaaf
2 changed files with 84 additions and 10 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2013-06-19 Richard Earnshaw <rearnsha@arm.com>
arm.md (split for eq(reg, 0)): Add variants for ARMv5 and Thumb2.
(peepholes for eq(reg, not-0)): Ensure condition register is dead after
pattern. Use more efficient sequences on ARMv5 and Thumb2.
2013-06-19 Steven Bosscher <steven@gcc.gnu.org>
PR target/57609

88
gcc/config/arm/arm.md
View File

@ -10016,6 +10016,16 @@
[(set (match_dup 0) (not:SI (match_dup 1)))
(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 31)))])
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
(eq:SI (match_operand:SI 1 "s_register_operand" "")
(const_int 0)))
(clobber (reg:CC CC_REGNUM))]
"arm_arch5 && TARGET_32BIT"
[(set (match_dup 0) (clz:SI (match_dup 1)))
(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))]
)
(define_split
[(set (match_operand:SI 0 "s_register_operand" "")
(eq:SI (match_operand:SI 1 "s_register_operand" "")
@ -10090,6 +10100,68 @@
;; Attempt to improve the sequence generated by the compare_scc splitters
;; not to use conditional execution.
;; Rd = (eq (reg1) (const_int0)) // ARMv5
;; clz Rd, reg1
;; lsr Rd, Rd, #5
(define_peephole2
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 1 "register_operand" "")
(const_int 0)))
(cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
(set (match_operand:SI 0 "register_operand" "") (const_int 0)))
(cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
(set (match_dup 0) (const_int 1)))]
"arm_arch5 && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)"
[(set (match_dup 0) (clz:SI (match_dup 1)))
(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))]
)
;; Rd = (eq (reg1) (const_int0)) // !ARMv5
;; negs Rd, reg1
;; adc Rd, Rd, reg1
(define_peephole2
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 1 "register_operand" "")
(const_int 0)))
(cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
(set (match_operand:SI 0 "register_operand" "") (const_int 0)))
(cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
(set (match_dup 0) (const_int 1)))
(match_scratch:SI 2 "r")]
"TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)"
[(parallel
[(set (reg:CC CC_REGNUM)
(compare:CC (const_int 0) (match_dup 1)))
(set (match_dup 2) (minus:SI (const_int 0) (match_dup 1)))])
(set (match_dup 0)
(plus:SI (plus:SI (match_dup 1) (match_dup 2))
(geu:SI (reg:CC CC_REGNUM) (const_int 0))))]
)
;; Rd = (eq (reg1) (reg2/imm)) // ARMv5
;; sub Rd, Reg1, reg2
;; clz Rd, Rd
;; lsr Rd, Rd, #5
(define_peephole2
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 1 "register_operand" "")
(match_operand:SI 2 "arm_rhs_operand" "")))
(cond_exec (ne (reg:CC CC_REGNUM) (const_int 0))
(set (match_operand:SI 0 "register_operand" "") (const_int 0)))
(cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
(set (match_dup 0) (const_int 1)))]
"arm_arch5 && TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)"
[(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
(set (match_dup 0) (clz:SI (match_dup 0)))
(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 5)))]
)
;; Rd = (eq (reg1) (reg2/imm)) // ! ARMv5
;; sub T1, Reg1, reg2
;; negs Rd, T1
;; adc Rd, Rd, T1
(define_peephole2
[(set (reg:CC CC_REGNUM)
(compare:CC (match_operand:SI 1 "register_operand" "")
@ -10099,20 +10171,16 @@
(cond_exec (eq (reg:CC CC_REGNUM) (const_int 0))
(set (match_dup 0) (const_int 1)))
(match_scratch:SI 3 "r")]
"TARGET_32BIT"
[(parallel
[(set (reg:CC CC_REGNUM)
(compare:CC (match_dup 1) (match_dup 2)))
(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))])
"TARGET_32BIT && peep2_regno_dead_p (3, CC_REGNUM)"
[(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
(parallel
[(set (reg:CC CC_REGNUM)
(compare:CC (const_int 0) (match_dup 3)))
(set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))])
(parallel
[(set (match_dup 0)
(plus:SI (plus:SI (match_dup 0) (match_dup 3))
(geu:SI (reg:CC CC_REGNUM) (const_int 0))))
(clobber (reg:CC CC_REGNUM))])])
(set (match_dup 0)
(plus:SI (plus:SI (match_dup 0) (match_dup 3))
(geu:SI (reg:CC CC_REGNUM) (const_int 0))))]
)
(define_insn "*cond_move"
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r")