[RS6000] Migrate from reduc_xxx to reduc_xxx_scal optabs
* config/rs6000/altivec.md (reduc_splus_<mode>): Rename to... (reduc_plus_scal_<mode>): ...this, add rs6000_expand_vector_extract. (reduc_uplus_v16qi): Remove. * config/rs6000/vector.md (VEC_reduc_name): Change "splus" to "plus". (reduc_<VEC_reduc_name>_v2df): Remove. (reduc_<VEC_reduc_name>_v4sf): Remove. (reduc_<VEC_reduc:VEC_reduc_name>_scal_<VEC_F:name>): New. * config/rs6000/vsx.md (vsx_reduc_<VEC_reduc_name>_v2df): Declare gen_ function by removing * prefix. (vsx_reduc_<VEC_reduc_name>_v4sf): Likewise. From-SVN: r227965
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@ -1,3 +1,18 @@
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2015-09-21 Alan Lawrence <alan.lawrence@arm.com>
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* config/rs6000/altivec.md (reduc_splus_<mode>): Rename to...
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(reduc_plus_scal_<mode>): ...this, add rs6000_expand_vector_extract.
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(reduc_uplus_v16qi): Remove.
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* config/rs6000/vector.md (VEC_reduc_name): Change "splus" to "plus".
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(reduc_<VEC_reduc_name>_v2df): Remove.
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(reduc_<VEC_reduc_name>_v4sf): Remove.
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(reduc_<VEC_reduc:VEC_reduc_name>_scal_<VEC_F:name>): New.
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* config/rs6000/vsx.md (vsx_reduc_<VEC_reduc_name>_v2df): Declare
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gen_ function by removing * prefix.
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(vsx_reduc_<VEC_reduc_name>_v4sf): Likewise.
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2015-09-21 Manuel López-Ibáñez <manu@gcc.gnu.org>
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PR middle-end/60832
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@ -2658,35 +2658,22 @@
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operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
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})
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(define_expand "reduc_splus_<mode>"
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[(set (match_operand:VIshort 0 "register_operand" "=v")
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(define_expand "reduc_plus_scal_<mode>"
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[(set (match_operand:<VI_scalar> 0 "register_operand" "=v")
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(unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
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UNSPEC_REDUC_PLUS))]
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"TARGET_ALTIVEC"
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{
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rtx vzero = gen_reg_rtx (V4SImode);
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rtx vtmp1 = gen_reg_rtx (V4SImode);
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rtx dest = gen_lowpart (V4SImode, operands[0]);
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rtx vtmp2 = gen_reg_rtx (<MODE>mode);
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rtx dest = gen_lowpart (V4SImode, vtmp2);
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int elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (<MODE>mode) - 1 : 0;
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emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
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emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
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emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero));
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DONE;
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})
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(define_expand "reduc_uplus_v16qi"
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[(set (match_operand:V16QI 0 "register_operand" "=v")
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(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
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UNSPEC_REDUC_PLUS))]
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"TARGET_ALTIVEC"
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{
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rtx vzero = gen_reg_rtx (V4SImode);
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rtx vtmp1 = gen_reg_rtx (V4SImode);
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rtx dest = gen_lowpart (V4SImode, operands[0]);
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emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
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emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
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emit_insn (gen_altivec_vsumsws_direct (dest, vtmp1, vzero));
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rs6000_expand_vector_extract (operands[0], vtmp2, elt);
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DONE;
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})
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@ -78,7 +78,7 @@
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;; Vector reduction code iterators
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(define_code_iterator VEC_reduc [plus smin smax])
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(define_code_attr VEC_reduc_name [(plus "splus")
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(define_code_attr VEC_reduc_name [(plus "plus")
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(smin "smin")
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(smax "smax")])
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@ -1061,38 +1061,29 @@
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"")
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;; Vector reduction expanders for VSX
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(define_expand "reduc_<VEC_reduc_name>_v2df"
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[(parallel [(set (match_operand:V2DF 0 "vfloat_operand" "")
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(VEC_reduc:V2DF
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(vec_concat:V2DF
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(vec_select:DF
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(match_operand:V2DF 1 "vfloat_operand" "")
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(parallel [(const_int 1)]))
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(vec_select:DF
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(match_dup 1)
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(parallel [(const_int 0)])))
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(match_dup 1)))
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(clobber (match_scratch:V2DF 2 ""))])]
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"VECTOR_UNIT_VSX_P (V2DFmode)"
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"")
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; The (VEC_reduc:V4SF
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; The (VEC_reduc:...
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; (op1)
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; (unspec:V4SF [(const_int 0)] UNSPEC_REDUC))
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; (unspec:... [(const_int 0)] UNSPEC_REDUC))
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;
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; is to allow us to use a code iterator, but not completely list all of the
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; vector rotates, etc. to prevent canonicalization
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(define_expand "reduc_<VEC_reduc_name>_v4sf"
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[(parallel [(set (match_operand:V4SF 0 "vfloat_operand" "")
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(VEC_reduc:V4SF
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(unspec:V4SF [(const_int 0)] UNSPEC_REDUC)
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(match_operand:V4SF 1 "vfloat_operand" "")))
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(clobber (match_scratch:V4SF 2 ""))
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(clobber (match_scratch:V4SF 3 ""))])]
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"VECTOR_UNIT_VSX_P (V4SFmode)"
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"")
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(define_expand "reduc_<VEC_reduc:VEC_reduc_name>_scal_<VEC_F:mode>"
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[(match_operand:<VEC_base> 0 "register_operand" "")
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(VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
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(unspec:VEC_F [(const_int 0)] UNSPEC_REDUC))]
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"VECTOR_UNIT_VSX_P (<VEC_F:MODE>mode)"
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{
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rtx vec = gen_reg_rtx (<VEC_F:MODE>mode);
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rtx elt = BYTES_BIG_ENDIAN
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? gen_int_mode (GET_MODE_NUNITS (<VEC_F:MODE>mode) - 1, QImode)
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: const0_rtx;
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emit_insn (gen_vsx_reduc_<VEC_reduc:VEC_reduc_name>_<VEC_F:mode> (vec,
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operand1));
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emit_insn (gen_vsx_extract_<VEC_F:mode> (operand0, vec, elt));
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DONE;
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})
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;;; Expanders for vector insn patterns shared between the SPE and TARGET_PAIRED systems.
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@ -2289,7 +2289,7 @@
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;; Vector reduction insns and splitters
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(define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v2df"
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(define_insn_and_split "vsx_reduc_<VEC_reduc_name>_v2df"
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[(set (match_operand:V2DF 0 "vfloat_operand" "=&wd,&?wa,wd,?wa")
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(VEC_reduc:V2DF
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(vec_concat:V2DF
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@ -2317,7 +2317,7 @@
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[(set_attr "length" "8")
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(set_attr "type" "veccomplex")])
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(define_insn_and_split "*vsx_reduc_<VEC_reduc_name>_v4sf"
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(define_insn_and_split "vsx_reduc_<VEC_reduc_name>_v4sf"
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[(set (match_operand:V4SF 0 "vfloat_operand" "=wf,?wa")
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(VEC_reduc:V4SF
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(unspec:V4SF [(const_int 0)] UNSPEC_REDUC)
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