backport: re PR target/81593 (Optimize PowerPC vector set from vector extract)
[gcc] 2017-08-29 Michael Meissner <meissner@linux.vnet.ibm.com> Back port from trunk 2017-08-07 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/81593 * config/rs6000/vsx.md (vsx_concat_<mode>_1): New combiner insns to recognize inserting into a vector from a double word element that was extracted from another vector, and eliminate extra XXPERMDI instructions. (vsx_concat_<mode>_2): Likewise. (vsx_concat_<mode>_3): Likewise. (vsx_set_<mode>, VSX_D): Rewrite vector set in terms of vector concat to allow optimizing inserts from previous extracts. [gcc/testsuite] 2017-08-29 Michael Meissner <meissner@linux.vnet.ibm.com> Back port from trunk 2017-08-07 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/81593 * gcc.target/powerpc/vec-setup.h: New tests to test various combinations of setting up vectors of 2 double word elements. * gcc.target/powerpc/vec-setup-long.c: Likewise. * gcc.target/powerpc/vec-setup-double.c: Likewise. * gcc.target/powerpc/vec-setup-be-long.c: Likewise. * gcc.target/powerpc/vec-setup-be-double.c: Likewise. From-SVN: r251445
This commit is contained in:
Michael Meissner
Michael Meissner
parent
c2a251cd90
commit
5eebe567c3
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@ -1,3 +1,18 @@
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2017-08-29 Michael Meissner <meissner@linux.vnet.ibm.com>
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Back port from trunk
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2017-08-07 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/81593
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* config/rs6000/vsx.md (vsx_concat_<mode>_1): New combiner insns
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to recognize inserting into a vector from a double word element
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that was extracted from another vector, and eliminate extra
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XXPERMDI instructions.
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(vsx_concat_<mode>_2): Likewise.
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(vsx_concat_<mode>_3): Likewise.
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(vsx_set_<mode>, VSX_D): Rewrite vector set in terms of vector
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concat to allow optimizing inserts from previous extracts.
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2017-08-29 Alan Modra <amodra@gmail.com>
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Apply from mainline
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@ -2049,6 +2049,80 @@
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}
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[(set_attr "type" "vecperm")])
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;; Combiner patterns to allow creating XXPERMDI's to access either double
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;; word element in a vector register.
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(define_insn "*vsx_concat_<mode>_1"
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[(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>")
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(vec_concat:VSX_D
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(vec_select:<VS_scalar>
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(match_operand:VSX_D 1 "gpc_reg_operand" "<VSa>")
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(parallel [(match_operand:QI 2 "const_0_to_1_operand" "n")]))
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(match_operand:<VS_scalar> 3 "gpc_reg_operand" "<VSa>")))]
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"VECTOR_MEM_VSX_P (<MODE>mode)"
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{
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HOST_WIDE_INT dword = INTVAL (operands[2]);
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if (BYTES_BIG_ENDIAN)
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{
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operands[4] = GEN_INT (2*dword);
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return "xxpermdi %x0,%x1,%x3,%4";
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}
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else
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{
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operands[4] = GEN_INT (!dword);
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return "xxpermdi %x0,%x3,%x1,%4";
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}
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}
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[(set_attr "type" "vecperm")])
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(define_insn "*vsx_concat_<mode>_2"
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[(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>")
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(vec_concat:VSX_D
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(match_operand:<VS_scalar> 1 "gpc_reg_operand" "<VSa>")
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(vec_select:<VS_scalar>
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(match_operand:VSX_D 2 "gpc_reg_operand" "<VSa>")
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(parallel [(match_operand:QI 3 "const_0_to_1_operand" "n")]))))]
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"VECTOR_MEM_VSX_P (<MODE>mode)"
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{
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HOST_WIDE_INT dword = INTVAL (operands[3]);
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if (BYTES_BIG_ENDIAN)
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{
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operands[4] = GEN_INT (dword);
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return "xxpermdi %x0,%x1,%x2,%4";
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}
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else
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{
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operands[4] = GEN_INT (2 * !dword);
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return "xxpermdi %x0,%x2,%x1,%4";
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}
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}
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[(set_attr "type" "vecperm")])
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(define_insn "*vsx_concat_<mode>_3"
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[(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>")
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(vec_concat:VSX_D
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(vec_select:<VS_scalar>
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(match_operand:VSX_D 1 "gpc_reg_operand" "<VSa>")
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(parallel [(match_operand:QI 2 "const_0_to_1_operand" "n")]))
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(vec_select:<VS_scalar>
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(match_operand:VSX_D 3 "gpc_reg_operand" "<VSa>")
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(parallel [(match_operand:QI 4 "const_0_to_1_operand" "n")]))))]
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"VECTOR_MEM_VSX_P (<MODE>mode)"
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{
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HOST_WIDE_INT dword1 = INTVAL (operands[2]);
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HOST_WIDE_INT dword2 = INTVAL (operands[4]);
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if (BYTES_BIG_ENDIAN)
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{
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operands[5] = GEN_INT ((2 * dword1) + dword2);
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return "xxpermdi %x0,%x1,%x3,%5";
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}
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else
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{
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operands[5] = GEN_INT ((2 * !dword2) + !dword1);
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return "xxpermdi %x0,%x3,%x1,%5";
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}
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}
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[(set_attr "type" "vecperm")])
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;; Special purpose concat using xxpermdi to glue two single precision values
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;; together, relying on the fact that internally scalar floats are represented
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;; as doubles. This is used to initialize a V4SF vector with 4 floats
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@ -2249,25 +2323,35 @@
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DONE;
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})
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;; Set the element of a V2DI/VD2F mode
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(define_insn "vsx_set_<mode>"
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[(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?<VSa>")
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(unspec:VSX_D
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[(match_operand:VSX_D 1 "vsx_register_operand" "wd,<VSa>")
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(match_operand:<VS_scalar> 2 "vsx_register_operand" "<VS_64reg>,<VSa>")
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(match_operand:QI 3 "u5bit_cint_operand" "i,i")]
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UNSPEC_VSX_SET))]
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;; Rewrite V2DF/V2DI set in terms of VEC_CONCAT
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(define_expand "vsx_set_<mode>"
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[(use (match_operand:VSX_D 0 "vsx_register_operand"))
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(use (match_operand:VSX_D 1 "vsx_register_operand"))
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(use (match_operand:<VS_scalar> 2 "gpc_reg_operand"))
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(use (match_operand:QI 3 "const_0_to_1_operand"))]
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"VECTOR_MEM_VSX_P (<MODE>mode)"
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{
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int idx_first = BYTES_BIG_ENDIAN ? 0 : 1;
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if (INTVAL (operands[3]) == idx_first)
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return \"xxpermdi %x0,%x2,%x1,1\";
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else if (INTVAL (operands[3]) == 1 - idx_first)
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return \"xxpermdi %x0,%x1,%x2,0\";
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rtx dest = operands[0];
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rtx vec_reg = operands[1];
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rtx value = operands[2];
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rtx ele = operands[3];
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rtx tmp = gen_reg_rtx (<VS_scalar>mode);
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if (ele == const0_rtx)
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{
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emit_insn (gen_vsx_extract_<mode> (tmp, vec_reg, const1_rtx));
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emit_insn (gen_vsx_concat_<mode> (dest, value, tmp));
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DONE;
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}
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else if (ele == const1_rtx)
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{
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emit_insn (gen_vsx_extract_<mode> (tmp, vec_reg, const0_rtx));
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emit_insn (gen_vsx_concat_<mode> (dest, tmp, value));
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DONE;
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}
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else
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gcc_unreachable ();
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}
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[(set_attr "type" "vecperm")])
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})
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;; Extract a DF/DI element from V2DF/V2DI
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;; Optimize cases were we can do a simple or direct move.
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@ -1,3 +1,19 @@
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2017-08-29 Michael Meissner <meissner@linux.vnet.ibm.com>
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Back port from trunk
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2017-08-07 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/81593
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* gcc.target/powerpc/vec-setup.h: New tests to test various
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combinations of setting up vectors of 2 double word elements.
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* gcc.target/powerpc/vec-setup-long.c: Likewise.
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* gcc.target/powerpc/vec-setup-double.c: Likewise.
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* gcc.target/powerpc/vec-setup-be-long.c: Likewise.
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* gcc.target/powerpc/vec-setup-be-double.c: Likewise.
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* gcc.target/powerpc/vsx-extract-6.c: New tests for optimzing
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vector inserts from vector extracts.
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* gcc.target/powerpc/vsx-extract-7.c: Likewise.
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2017-08-29 Richard Biener <rguenther@suse.de>
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Backport from mainline
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@ -0,0 +1,12 @@
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/* { dg-do run { target { powerpc*-*-linux* } } } */
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/* { dg-require-effective-target vsx_hw } */
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/* { dg-options "-O2 -mvsx" } */
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/* Test various ways of creating vectors with 2 double words and accessing the
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elements. This test uses the double datatype.
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This test explicitly tests -maltivec=be to make sure things are correct. */
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#define DO_DOUBLE
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#include "vec-setup.h"
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/* { dg-do run { target { powerpc64le*-*-linux* } } } */
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/* { dg-require-effective-target vsx_hw } */
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/* { dg-options "-O2 -mvsx -maltivec=be" } */
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/* Test various ways of creating vectors with 2 double words and accessing the
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elements. This test uses the long (on 64-bit systems) or long long datatype
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(on 32-bit systems).
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This test explicitly tests -maltivec=be to make sure things are correct. */
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#include "vec-setup.h"
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/* { dg-do run { target { powerpc*-*-linux* } } } */
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/* { dg-require-effective-target vsx_hw } */
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/* { dg-options "-O2 -mvsx" } */
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/* Test various ways of creating vectors with 2 double words and accessing the
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elements. This test uses the double datatype and the default endian
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order. */
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#define DO_DOUBLE
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#include "vec-setup.h"
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/* { dg-do run { target { powerpc*-*-linux* } } } */
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/* { dg-require-effective-target vsx_hw } */
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/* { dg-options "-O2 -mvsx" } */
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/* Test various ways of creating vectors with 2 double words and accessing the
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elements. This test uses the long (on 64-bit systems) or long long datatype
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(on 32-bit systems). The default endian order is used. */
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#include "vec-setup.h"
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#include <altivec.h>
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/* Test various ways of creating vectors with 2 double words and accessing the
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elements. This include files supports:
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testing double
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testing long on 64-bit systems
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testing long long on 32-bit systems.
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The endian support is:
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big endian
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little endian with little endian element ordering
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little endian with big endian element ordering. */
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#ifdef DEBUG
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#include <stdio.h>
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#define DEBUG0(STR) fputs (STR, stdout)
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#define DEBUG2(STR,A,B) printf (STR, A, B)
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static int errors = 0;
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#else
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#include <stdlib.h>
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#define DEBUG0(STR)
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#define DEBUG2(STR,A,B)
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#endif
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#if defined(DO_DOUBLE)
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#define TYPE double
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#define STYPE "double"
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#define ZERO 0.0
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#define ONE 1.0
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#define TWO 2.0
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#define THREE 3.0
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#define FOUR 4.0
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#define FIVE 5.0
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#define SIX 6.0
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#define FMT "g"
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#elif defined(_ARCH_PPC64)
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#define TYPE long
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#define STYPE "long"
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#define ZERO 0L
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#define ONE 1L
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#define TWO 2L
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#define THREE 3L
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#define FOUR 4L
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#define FIVE 5L
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#define SIX 6L
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#define FMT "ld"
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#else
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#define TYPE long long
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#define STYPE "long long"
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#define ZERO 0LL
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#define ONE 1LL
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#define TWO 2LL
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#define THREE 3LL
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#define FOUR 4LL
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#define FIVE 5LL
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#define SIX 6LL
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#define FMT "lld"
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#endif
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/* Macros to order the left/right values correctly. Note, -maltivec=be does
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not change the order for static initializations, so we have to handle it
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specially. */
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#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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#define INIT_ORDER(A, B) (TYPE) A, (TYPE) B
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#define ELEMENT_ORDER(A, B) (TYPE) A, (TYPE) B
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#define ENDIAN "-mbig"
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#elif __VEC_ELEMENT_REG_ORDER__ == __ORDER_BIG_ENDIAN__
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#define NO_ARRAY
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#define INIT_ORDER(A, B) (TYPE) B, (TYPE) A
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#define ELEMENT_ORDER(A, B) (TYPE) A, (TYPE) B
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#define ENDIAN "-mlittle -maltivec=be"
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#else
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#define INIT_ORDER(A, B) (TYPE) B, (TYPE) A
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#define ELEMENT_ORDER(A, B) (TYPE) B, (TYPE) A
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#define ENDIAN "-mlittle"
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#endif
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static volatile TYPE five = FIVE;
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static volatile TYPE six = SIX;
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static volatile vector TYPE s_v12 = { ONE, TWO };
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static volatile vector TYPE g_v34 = { THREE, FOUR };
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__attribute__((__noinline__))
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static void
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vector_check (vector TYPE v, TYPE expect_hi, TYPE expect_lo)
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{
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TYPE actual_hi, actual_lo;
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#ifdef DEBUG
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const char *pass_fail;
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#endif
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__asm__ ("xxlor %x0,%x1,%x1" : "=&wa" (actual_hi) : "wa" (v));
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__asm__ ("xxpermdi %x0,%x1,%x1,3" : "=&wa" (actual_lo) : "wa" (v));
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#ifdef DEBUG
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if ((actual_hi == expect_hi) && (actual_lo == expect_lo))
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pass_fail = ", pass";
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else
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{
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pass_fail = ", fail";
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errors++;
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}
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printf ("Expected %" FMT ", %" FMT ", got %" FMT ", %" FMT "%s\n",
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expect_hi, expect_lo,
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actual_hi, actual_lo,
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pass_fail);
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#else
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if ((actual_hi != expect_hi) || (actual_lo != expect_lo))
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abort ();
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#endif
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}
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__attribute__((__noinline__))
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static vector TYPE
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combine (TYPE op0, TYPE op1)
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{
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return (vector TYPE) { op0, op1 };
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}
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__attribute__((__noinline__))
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static vector TYPE
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combine_insert (TYPE op0, TYPE op1)
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{
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vector TYPE ret = (vector TYPE) { ZERO, ZERO };
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ret = vec_insert (op0, ret, 0);
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ret = vec_insert (op1, ret, 1);
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return ret;
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}
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__attribute__((__noinline__))
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static vector TYPE
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concat_extract_00 (vector TYPE a, vector TYPE b)
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{
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return (vector TYPE) { vec_extract (a, 0), vec_extract (b, 0) };
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}
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__attribute__((__noinline__))
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static vector TYPE
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concat_extract_01 (vector TYPE a, vector TYPE b)
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{
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return (vector TYPE) { vec_extract (a, 0), vec_extract (b, 1) };
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}
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__attribute__((__noinline__))
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static vector TYPE
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concat_extract_10 (vector TYPE a, vector TYPE b)
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{
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return (vector TYPE) { vec_extract (a, 1), vec_extract (b, 0) };
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}
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__attribute__((__noinline__))
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static vector TYPE
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concat_extract_11 (vector TYPE a, vector TYPE b)
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{
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return (vector TYPE) { vec_extract (a, 1), vec_extract (b, 1) };
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}
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__attribute__((__noinline__))
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static vector TYPE
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concat_extract2_0s (vector TYPE a, TYPE b)
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{
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return (vector TYPE) { vec_extract (a, 0), b };
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}
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__attribute__((__noinline__))
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static vector TYPE
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concat_extract2_1s (vector TYPE a, TYPE b)
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{
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return (vector TYPE) { vec_extract (a, 1), b };
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}
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__attribute__((__noinline__))
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static vector TYPE
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concat_extract2_s0 (TYPE a, vector TYPE b)
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{
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return (vector TYPE) { a, vec_extract (b, 0) };
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}
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__attribute__((__noinline__))
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static vector TYPE
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concat_extract2_s1 (TYPE a, vector TYPE b)
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{
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return (vector TYPE) { a, vec_extract (b, 1) };
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}
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__attribute__((__noinline__))
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static vector TYPE
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concat_extract_nn (vector TYPE a, vector TYPE b, size_t i, size_t j)
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{
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return (vector TYPE) { vec_extract (a, i), vec_extract (b, j) };
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}
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|
||||
#ifndef NO_ARRAY
|
||||
__attribute__((__noinline__))
|
||||
static vector TYPE
|
||||
array_0 (vector TYPE v, TYPE a)
|
||||
{
|
||||
v[0] = a;
|
||||
return v;
|
||||
}
|
||||
|
||||
__attribute__((__noinline__))
|
||||
static vector TYPE
|
||||
array_1 (vector TYPE v, TYPE a)
|
||||
{
|
||||
v[1] = a;
|
||||
return v;
|
||||
}
|
||||
|
||||
__attribute__((__noinline__))
|
||||
static vector TYPE
|
||||
array_01 (vector TYPE v, TYPE a, TYPE b)
|
||||
{
|
||||
v[0] = a;
|
||||
v[1] = b;
|
||||
return v;
|
||||
}
|
||||
|
||||
__attribute__((__noinline__))
|
||||
static vector TYPE
|
||||
array_01b (TYPE a, TYPE b)
|
||||
{
|
||||
vector TYPE v = (vector TYPE) { 0, 0 };
|
||||
v[0] = a;
|
||||
v[1] = b;
|
||||
return v;
|
||||
}
|
||||
#endif
|
||||
|
||||
int
|
||||
main (void)
|
||||
{
|
||||
vector TYPE a = (vector TYPE) { ONE, TWO };
|
||||
vector TYPE b = (vector TYPE) { THREE, FOUR };
|
||||
size_t i, j;
|
||||
|
||||
#ifndef NO_ARRAY
|
||||
vector TYPE z = (vector TYPE) { ZERO, ZERO };
|
||||
#endif
|
||||
|
||||
DEBUG2 ("Endian: %s, type: %s\n", ENDIAN, STYPE);
|
||||
DEBUG0 ("\nStatic/global initialization\n");
|
||||
vector_check (s_v12, INIT_ORDER (1, 2));
|
||||
vector_check (g_v34, INIT_ORDER (3, 4));
|
||||
|
||||
DEBUG0 ("\nVector via constant runtime intiialization\n");
|
||||
vector_check (a, INIT_ORDER (1, 2));
|
||||
vector_check (b, INIT_ORDER (3, 4));
|
||||
|
||||
DEBUG0 ("\nCombine scalars using vector initialization\n");
|
||||
vector_check (combine (1, 2), INIT_ORDER (1, 2));
|
||||
vector_check (combine (3, 4), INIT_ORDER (3, 4));
|
||||
|
||||
DEBUG0 ("\nSetup with vec_insert\n");
|
||||
a = combine_insert (1, 2);
|
||||
b = combine_insert (3, 4);
|
||||
vector_check (a, ELEMENT_ORDER (1, 2));
|
||||
vector_check (b, ELEMENT_ORDER (3, 4));
|
||||
|
||||
#ifndef NO_ARRAY
|
||||
DEBUG0 ("\nTesting array syntax\n");
|
||||
vector_check (array_0 (a, FIVE), ELEMENT_ORDER (5, 2));
|
||||
vector_check (array_1 (b, SIX), ELEMENT_ORDER (3, 6));
|
||||
vector_check (array_01 (z, FIVE, SIX), ELEMENT_ORDER (5, 6));
|
||||
vector_check (array_01b (FIVE, SIX), ELEMENT_ORDER (5, 6));
|
||||
|
||||
vector_check (array_0 (a, five), ELEMENT_ORDER (5, 2));
|
||||
vector_check (array_1 (b, six), ELEMENT_ORDER (3, 6));
|
||||
vector_check (array_01 (z, five, six), ELEMENT_ORDER (5, 6));
|
||||
vector_check (array_01b (five, six), ELEMENT_ORDER (5, 6));
|
||||
#else
|
||||
DEBUG0 ("\nSkipping array syntax on -maltivec=be\n");
|
||||
#endif
|
||||
|
||||
DEBUG0 ("\nTesting concat and extract\n");
|
||||
vector_check (concat_extract_00 (a, b), INIT_ORDER (1, 3));
|
||||
vector_check (concat_extract_01 (a, b), INIT_ORDER (1, 4));
|
||||
vector_check (concat_extract_10 (a, b), INIT_ORDER (2, 3));
|
||||
vector_check (concat_extract_11 (a, b), INIT_ORDER (2, 4));
|
||||
|
||||
DEBUG0 ("\nTesting concat and extract #2\n");
|
||||
vector_check (concat_extract2_0s (a, FIVE), INIT_ORDER (1, 5));
|
||||
vector_check (concat_extract2_1s (a, FIVE), INIT_ORDER (2, 5));
|
||||
vector_check (concat_extract2_s0 (SIX, a), INIT_ORDER (6, 1));
|
||||
vector_check (concat_extract2_s1 (SIX, a), INIT_ORDER (6, 2));
|
||||
|
||||
DEBUG0 ("\nTesting variable concat and extract\n");
|
||||
for (i = 0; i < 2; i++)
|
||||
{
|
||||
for (j = 0; j < 2; j++)
|
||||
{
|
||||
static struct {
|
||||
TYPE hi;
|
||||
TYPE lo;
|
||||
} hilo[2][2] =
|
||||
{ { { ONE, THREE }, { ONE, FOUR } },
|
||||
{ { TWO, THREE }, { TWO, FOUR } } };
|
||||
|
||||
vector_check (concat_extract_nn (a, b, i, j),
|
||||
INIT_ORDER (hilo[i][j].hi, hilo[i][j].lo));
|
||||
}
|
||||
}
|
||||
|
||||
DEBUG0 ("\nTesting separate function\n");
|
||||
vector_check (combine (vec_extract (a, 0), vec_extract (b, 0)),
|
||||
INIT_ORDER (1, 3));
|
||||
|
||||
vector_check (combine (vec_extract (a, 0), vec_extract (b, 1)),
|
||||
INIT_ORDER (1, 4));
|
||||
|
||||
vector_check (combine (vec_extract (a, 1), vec_extract (b, 0)),
|
||||
INIT_ORDER (2, 3));
|
||||
|
||||
vector_check (combine (vec_extract (a, 1), vec_extract (b, 1)),
|
||||
INIT_ORDER (2, 4));
|
||||
|
||||
vector_check (combine_insert (vec_extract (a, 0), vec_extract (b, 0)),
|
||||
ELEMENT_ORDER (1, 3));
|
||||
|
||||
vector_check (combine_insert (vec_extract (a, 0), vec_extract (b, 1)),
|
||||
ELEMENT_ORDER (1, 4));
|
||||
|
||||
vector_check (combine_insert (vec_extract (a, 1), vec_extract (b, 0)),
|
||||
ELEMENT_ORDER (2, 3));
|
||||
|
||||
vector_check (combine_insert (vec_extract (a, 1), vec_extract (b, 1)),
|
||||
ELEMENT_ORDER (2, 4));
|
||||
|
||||
|
||||
#if defined(DO_DOUBLE)
|
||||
DEBUG0 ("\nTesting explicit 2df concat\n");
|
||||
vector_check (__builtin_vsx_concat_2df (FIVE, SIX), INIT_ORDER (5, 6));
|
||||
vector_check (__builtin_vsx_concat_2df (five, six), INIT_ORDER (5, 6));
|
||||
|
||||
#elif defined(_ARCH_PPC64)
|
||||
DEBUG0 ("\nTesting explicit 2di concat\n");
|
||||
vector_check (__builtin_vsx_concat_2di (FIVE, SIX), INIT_ORDER (5, 6));
|
||||
vector_check (__builtin_vsx_concat_2di (five, six), INIT_ORDER (5, 6));
|
||||
|
||||
#else
|
||||
DEBUG0 ("\nSkip explicit 2di concat on 32-bit\n");
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG
|
||||
if (errors)
|
||||
printf ("\n%d error%s were found", errors, (errors == 1) ? "" : "s");
|
||||
else
|
||||
printf ("\nNo errors were found.\n");
|
||||
|
||||
return errors;
|
||||
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
}
|
||||
Loading…
Reference in New Issue