i386.md (insv<mode>): Rename from insv.
* config/i386/i386.md (insv<mode>): Rename from insv. Use SWI48 modes for operands 0 and 3. Use SImode for operands 2 and 3. Copy operand 0 to a temporary if !ext_register_operand. Remove ancient extract_bit_field workaround. (insv<mode>_1): Rename from mov<mode>_insv_1. (*insvqi): Rename from *movqi_insv_2. * config/i386/i386.c (emit_i386_cw_initialization): Update calls for renamed insvsi_1. (promote_duplicated_reg): Ditto for renamed insv<mode>_1. From-SVN: r225484
This commit is contained in:
Uros Bizjak
Uros Bizjak
parent
c03b04168e
commit
5ef7cdf81c
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@ -1,3 +1,15 @@
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2015-07-06 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (insv<mode>): Rename from insv. Use SWI48
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modes for operands 0 and 3. Use SImode for operands 2 and 3.
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Copy operand 0 to a temporary if !ext_register_operand. Remove
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ancient extract_bit_field workaround.
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(insv<mode>_1): Rename from mov<mode>_insv_1.
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(*insvqi): Rename from *movqi_insv_2.
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* config/i386/i386.c (emit_i386_cw_initialization): Update calls
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for renamed insvsi_1.
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(promote_duplicated_reg): Ditto for renamed insv<mode>_1.
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2015-07-06 Nathan Sidwell <nathan@codesourcery.com>
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* config/nvptx/nvptx.c (nvptx_reorg): Remove unused vars. Fix
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@ -73,13 +85,13 @@
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Copy operand 1 to a temporary if !ext_register_operand. Remove
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ancient extract_bit_field workaround.
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(*extv<mode>): Rename from *mov<mode>_extv_1.
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(*extvqi): Rename from *movqi_extv_q.
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(*extvqi): Rename from *movqi_extv_1.
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(extzv<mode>): Rename from extzv. Use SWI248 modes for
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operands 0 and 1. Use SImode for operands 2 and 3. Copy operand 1
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to a temporary if !ext_register_operand. Remove ancient
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extract_bit_field workaround.
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(*extzv<mode>): Rename from *mov<mode>_extzv_1.
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(*extzvqi): Rename from *movqi_extzv_1.
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(*extzvqi): Rename from *movqi_extzv_2.
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(*testqi_ext_3): Remove modes from const_int_operand predicated
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operands. Add "n" constraint.
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(*btsq, *btrq, *btcq): Remove mode from const_0_to_63 predicated
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@ -17063,19 +17063,19 @@ emit_i387_cw_initialization (int mode)
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{
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case I387_CW_TRUNC:
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/* round toward zero (truncate) */
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emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc)));
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emit_insn (gen_insvsi_1 (reg, GEN_INT (0xc)));
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slot = SLOT_CW_TRUNC;
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break;
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case I387_CW_FLOOR:
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/* round down toward -oo */
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emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4)));
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emit_insn (gen_insvsi_1 (reg, GEN_INT (0x4)));
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slot = SLOT_CW_FLOOR;
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break;
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case I387_CW_CEIL:
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/* round up toward +oo */
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emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8)));
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emit_insn (gen_insvsi_1 (reg, GEN_INT (0x8)));
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slot = SLOT_CW_CEIL;
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break;
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@ -24834,9 +24834,9 @@ promote_duplicated_reg (machine_mode mode, rtx val)
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if (!TARGET_PARTIAL_REG_STALL)
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if (mode == SImode)
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emit_insn (gen_movsi_insv_1 (reg, reg));
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emit_insn (gen_insvsi_1 (reg, reg));
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else
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emit_insn (gen_movdi_insv_1 (reg, reg));
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emit_insn (gen_insvdi_1 (reg, reg));
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else
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{
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tmp = expand_simple_binop (mode, ASHIFT, reg, GEN_INT (8),
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@ -2780,7 +2780,37 @@
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(const_string "SI")
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(const_string "QI")))])
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(define_insn "mov<mode>_insv_1"
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(define_expand "insv<mode>"
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[(set (zero_extract:SWI48 (match_operand:SWI48 0 "register_operand")
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(match_operand:SI 1 "const_int_operand")
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(match_operand:SI 2 "const_int_operand"))
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(match_operand:SWI48 3 "register_operand"))]
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""
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{
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rtx dst;
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if (ix86_expand_pinsr (operands))
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DONE;
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/* Handle insertions to %ah et al. */
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if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
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FAIL;
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dst = operands[0];
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if (!ext_register_operand (dst, VOIDmode))
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dst = copy_to_reg (dst);
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emit_insn (gen_insv<mode>_1 (dst, operands[3]));
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/* Fix up the destination if needed. */
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if (dst != operands[0])
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emit_move_insn (operands[0], dst);
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DONE;
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})
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(define_insn "insv<mode>_1"
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[(set (zero_extract:SWI48 (match_operand 0 "ext_register_operand" "+Q,Q")
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(const_int 8)
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(const_int 8))
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@ -2795,7 +2825,7 @@
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(set_attr "type" "imov")
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(set_attr "mode" "QI")])
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(define_insn "*movqi_insv_2"
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(define_insn "*insvqi"
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[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
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(const_int 8)
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(const_int 8))
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@ -10608,34 +10638,6 @@
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;; Bit set / bit test instructions
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(define_expand "insv"
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[(set (zero_extract (match_operand 0 "register_operand")
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(match_operand 1 "const_int_operand")
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(match_operand 2 "const_int_operand"))
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(match_operand 3 "register_operand"))]
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""
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{
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rtx (*gen_mov_insv_1) (rtx, rtx);
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if (ix86_expand_pinsr (operands))
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DONE;
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/* Handle insertions to %ah et al. */
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if (INTVAL (operands[1]) != 8 || INTVAL (operands[2]) != 8)
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FAIL;
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/* From mips.md: insert_bit_field doesn't verify that our source
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matches the predicate, so check it again here. */
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if (! ext_register_operand (operands[0], VOIDmode))
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FAIL;
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gen_mov_insv_1 = (TARGET_64BIT
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? gen_movdi_insv_1 : gen_movsi_insv_1);
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emit_insn (gen_mov_insv_1 (operands[0], operands[3]));
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DONE;
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})
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;; %%% bts, btr, btc, bt.
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;; In general these instructions are *slow* when applied to memory,
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;; since they enforce atomic operation. When applied to registers,
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