aarch-cost-tables.h (cortexa53_extra_costs): New table.
* config/arm/aarch-cost-tables.h (cortexa53_extra_costs): New table. * config/arm/arm.c (arm_cortex_a53_tune): New. * config/arm/arm-cores.def (cortex-a53): Use cortex_a53 tuning struct. From-SVN: r204941
This commit is contained in:
Kyrylo Tkachov
Kyrylo Tkachov
parent
74bc175e84
commit
5f1b2f8bfb
@ -1,3 +1,9 @@
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2013-11-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
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* config/arm/aarch-cost-tables.h (cortexa53_extra_costs): New table.
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* config/arm/arm.c (arm_cortex_a53_tune): New.
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* config/arm/arm-cores.def (cortex-a53): Use cortex_a53 tuning struct.
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2013-11-12 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
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* config.gcc (i[34567]86-*-linux* | ...): Add bdver4.
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@ -122,5 +122,106 @@ const struct cpu_cost_table generic_extra_costs =
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}
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};
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const struct cpu_cost_table cortexa53_extra_costs =
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{
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/* ALU */
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{
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0, /* Arith. */
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0, /* Logical. */
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COSTS_N_INSNS (1), /* Shift. */
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COSTS_N_INSNS (2), /* Shift_reg. */
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COSTS_N_INSNS (1), /* Arith_shift. */
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COSTS_N_INSNS (2), /* Arith_shift_reg. */
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COSTS_N_INSNS (1), /* Log_shift. */
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COSTS_N_INSNS (2), /* Log_shift_reg. */
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0, /* Extend. */
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COSTS_N_INSNS (1), /* Extend_arith. */
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COSTS_N_INSNS (1), /* Bfi. */
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COSTS_N_INSNS (1), /* Bfx. */
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0, /* Clz. */
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0, /* non_exec. */
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true /* non_exec_costs_exec. */
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},
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{
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/* MULT SImode */
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{
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COSTS_N_INSNS (1), /* Simple. */
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COSTS_N_INSNS (2), /* Flag_setting. */
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COSTS_N_INSNS (1), /* Extend. */
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COSTS_N_INSNS (1), /* Add. */
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COSTS_N_INSNS (1), /* Extend_add. */
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COSTS_N_INSNS (7) /* Idiv. */
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},
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/* MULT DImode */
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{
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COSTS_N_INSNS (2), /* Simple. */
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0, /* Flag_setting (N/A). */
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COSTS_N_INSNS (2), /* Extend. */
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COSTS_N_INSNS (2), /* Add. */
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COSTS_N_INSNS (2), /* Extend_add. */
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COSTS_N_INSNS (15) /* Idiv. */
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}
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},
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/* LD/ST */
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{
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COSTS_N_INSNS (1), /* Load. */
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COSTS_N_INSNS (1), /* Load_sign_extend. */
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COSTS_N_INSNS (1), /* Ldrd. */
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COSTS_N_INSNS (1), /* Ldm_1st. */
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1, /* Ldm_regs_per_insn_1st. */
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2, /* Ldm_regs_per_insn_subsequent. */
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COSTS_N_INSNS (1), /* Loadf. */
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COSTS_N_INSNS (1), /* Loadd. */
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COSTS_N_INSNS (1), /* Load_unaligned. */
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0, /* Store. */
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0, /* Strd. */
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0, /* Stm_1st. */
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1, /* Stm_regs_per_insn_1st. */
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2, /* Stm_regs_per_insn_subsequent. */
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0, /* Storef. */
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0, /* Stored. */
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COSTS_N_INSNS (1) /* Store_unaligned. */
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},
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{
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/* FP SFmode */
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{
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COSTS_N_INSNS (15), /* Div. */
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COSTS_N_INSNS (3), /* Mult. */
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COSTS_N_INSNS (7), /* Mult_addsub. */
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COSTS_N_INSNS (7), /* Fma. */
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COSTS_N_INSNS (3), /* Addsub. */
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COSTS_N_INSNS (1), /* Fpconst. */
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COSTS_N_INSNS (2), /* Neg. */
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COSTS_N_INSNS (1), /* Compare. */
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COSTS_N_INSNS (3), /* Widen. */
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COSTS_N_INSNS (3), /* Narrow. */
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COSTS_N_INSNS (3), /* Toint. */
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COSTS_N_INSNS (3), /* Fromint. */
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COSTS_N_INSNS (3) /* Roundint. */
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},
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/* FP DFmode */
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{
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COSTS_N_INSNS (30), /* Div. */
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COSTS_N_INSNS (3), /* Mult. */
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COSTS_N_INSNS (7), /* Mult_addsub. */
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COSTS_N_INSNS (7), /* Fma. */
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COSTS_N_INSNS (3), /* Addsub. */
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COSTS_N_INSNS (1), /* Fpconst. */
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COSTS_N_INSNS (2), /* Neg. */
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COSTS_N_INSNS (1), /* Compare. */
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COSTS_N_INSNS (3), /* Widen. */
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COSTS_N_INSNS (3), /* Narrow. */
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COSTS_N_INSNS (3), /* Toint. */
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COSTS_N_INSNS (3), /* Fromint. */
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COSTS_N_INSNS (3) /* Roundint. */
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}
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},
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/* Vector */
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{
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COSTS_N_INSNS (1) /* Alu. */
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}
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};
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#endif /* GCC_AARCH_COST_TABLES_H */
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@ -129,7 +129,7 @@ ARM_CORE("cortex-a7", cortexa7, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV
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ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, cortex)
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ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9)
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ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, cortex_a15)
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ARM_CORE("cortex-a53", cortexa53, 8A, FL_LDSCHED, cortex)
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ARM_CORE("cortex-a53", cortexa53, 8A, FL_LDSCHED, cortex_a53)
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ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, cortex)
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ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, cortex)
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ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, cortex)
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@ -1405,6 +1405,22 @@ const struct tune_params arm_cortex_a15_tune =
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false /* Prefer Neon for 64-bits bitops. */
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};
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const struct tune_params arm_cortex_a53_tune =
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{
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arm_9e_rtx_costs,
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&cortexa53_extra_costs,
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NULL, /* Scheduler cost adjustment. */
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1, /* Constant limit. */
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5, /* Max cond insns. */
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ARM_PREFETCH_NOT_BENEFICIAL,
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false, /* Prefer constant pool. */
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arm_default_branch_cost,
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false, /* Prefer LDRD/STRD. */
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{true, true}, /* Prefer non short circuit. */
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&arm_default_vec_cost, /* Vectorizer costs. */
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false /* Prefer Neon for 64-bits bitops. */
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};
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/* Branches can be dual-issued on Cortex-A5, so conditional execution is
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less appealing. Set max_insns_skipped to a low value. */
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