[ARM] Add patterns for new instructions
* config/arm/iterators.md (VQRDMLH_AS): New. (neon_rdma_as): New. * config/arm/neon.md (neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h<mode>): New. (neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h_lane<mode>): New. * config/arm/unspecs.md (UNSPEC_VQRDMLAH): New. (UNSPEC_VQRDMLSH): New. From-SVN: r231681
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@ -1,3 +1,13 @@
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2015-12-16 Matthew Wahab <matthew.wahab@arm.com>
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* config/arm/iterators.md (VQRDMLH_AS): New.
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(neon_rdma_as): New.
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* config/arm/neon.md
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(neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h<mode>): New.
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(neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h_lane<mode>): New.
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* config/arm/unspecs.md (UNSPEC_VQRDMLAH): New.
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(UNSPEC_VQRDMLSH): New.
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2015-12-16 Matthew Wahab <matthew.wahab@arm.com>
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* config/arm/t-aprofile: Make "armv8.1-a" and "armv8.1-a+crc"
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@ -362,6 +362,8 @@
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(define_int_iterator CRYPTO_SELECTING [UNSPEC_SHA1C UNSPEC_SHA1M
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UNSPEC_SHA1P])
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(define_int_iterator VQRDMLH_AS [UNSPEC_VQRDMLAH UNSPEC_VQRDMLSH])
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;;----------------------------------------------------------------------------
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;; Mode attributes
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;;----------------------------------------------------------------------------
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@ -831,3 +833,6 @@
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(simple_return " && use_simple_return_p ()")])
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(define_code_attr return_cond_true [(return " && USE_RETURN_INSN (TRUE)")
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(simple_return " && use_simple_return_p ()")])
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;; Attributes for VQRDMLAH/VQRDMLSH
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(define_int_attr neon_rdma_as [(UNSPEC_VQRDMLAH "a") (UNSPEC_VQRDMLSH "s")])
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@ -2014,6 +2014,18 @@
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[(set_attr "type" "neon_sat_mul_<V_elem_ch><q>")]
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)
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;; vqrdmlah, vqrdmlsh
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(define_insn "neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h<mode>"
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[(set (match_operand:VMDQI 0 "s_register_operand" "=w")
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(unspec:VMDQI [(match_operand:VMDQI 1 "s_register_operand" "0")
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(match_operand:VMDQI 2 "s_register_operand" "w")
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(match_operand:VMDQI 3 "s_register_operand" "w")]
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VQRDMLH_AS))]
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"TARGET_NEON_RDMA"
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"vqrdml<VQRDMLH_AS:neon_rdma_as>h.<V_s_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
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[(set_attr "type" "neon_sat_mla_<V_elem_ch>_long")]
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)
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(define_insn "neon_vqdmlal<mode>"
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[(set (match_operand:<V_widen> 0 "s_register_operand" "=w")
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(unspec:<V_widen> [(match_operand:<V_widen> 1 "s_register_operand" "0")
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@ -3176,6 +3188,39 @@ if (BYTES_BIG_ENDIAN)
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[(set_attr "type" "neon_sat_mul_<V_elem_ch>_scalar_q")]
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)
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;; vqrdmlah_lane, vqrdmlsh_lane
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(define_insn "neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h_lane<mode>"
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[(set (match_operand:VMQI 0 "s_register_operand" "=w")
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(unspec:VMQI [(match_operand:VMQI 1 "s_register_operand" "0")
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(match_operand:VMQI 2 "s_register_operand" "w")
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(match_operand:<V_HALF> 3 "s_register_operand"
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"<scalar_mul_constraint>")
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(match_operand:SI 4 "immediate_operand" "i")]
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VQRDMLH_AS))]
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"TARGET_NEON_RDMA"
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{
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return
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"vqrdml<VQRDMLH_AS:neon_rdma_as>h.<V_s_elem>\t%q0, %q2, %P3[%c4]";
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}
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[(set_attr "type" "neon_mla_<V_elem_ch>_scalar<q>")]
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)
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(define_insn "neon_vqrdml<VQRDMLH_AS:neon_rdma_as>h_lane<mode>"
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[(set (match_operand:VMDI 0 "s_register_operand" "=w")
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(unspec:VMDI [(match_operand:VMDI 1 "s_register_operand" "0")
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(match_operand:VMDI 2 "s_register_operand" "w")
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(match_operand:VMDI 3 "s_register_operand"
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"<scalar_mul_constraint>")
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(match_operand:SI 4 "immediate_operand" "i")]
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VQRDMLH_AS))]
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"TARGET_NEON_RDMA"
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{
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return
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"vqrdml<VQRDMLH_AS:neon_rdma_as>h.<V_s_elem>\t%P0, %P2, %P3[%c4]";
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}
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[(set_attr "type" "neon_mla_<V_elem_ch>_scalar")]
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)
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(define_insn "neon_vmla_lane<mode>"
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[(set (match_operand:VMD 0 "s_register_operand" "=w")
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(unspec:VMD [(match_operand:VMD 1 "s_register_operand" "0")
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@ -360,5 +360,7 @@
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UNSPEC_NVRINTX
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UNSPEC_NVRINTA
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UNSPEC_NVRINTN
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UNSPEC_VQRDMLAH
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UNSPEC_VQRDMLSH
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])
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