rs6000.c (struct processor_cost): Change l1_cache_lines to l1_cache_size.
* config/rs6000/rs6000.c (struct processor_cost): Change l1_cache_lines to l1_cache_size. Add l2_cache_size. (*_cost): Convert l1 cache information to kilobytes. Add l2 cache information. (rios1_costs, rios2_cost): Correct cache line size. (rs6000_override_options): Set l2-cache-size parameter. From-SVN: r127181
This commit is contained in:
David Edelsohn
parent
737b089116
commit
5f732aba81
@ -1,3 +1,12 @@
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2007-08-03 David Edelsohn <edelsohn@gnu.org>
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* config/rs6000/rs6000.c (struct processor_cost): Change
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l1_cache_lines to l1_cache_size. Add l2_cache_size.
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(*_cost): Convert l1 cache information to kilobytes. Add l2 cache
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information.
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(rios1_costs, rios2_cost): Correct cache line size.
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(rs6000_override_options): Set l2-cache-size parameter.
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2007-08-03 Andrew Pinski <andrew_pinski@playstation.sony.com>
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Diego Novillo <dnovillo@google.com>
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@ -20529,7 +20538,7 @@
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* langhooks.h (struct lang_hooks): Removed field
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'can_use_bit_fields_p'.
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2007-01-10 Ralf Corsépius <ralf.corsepius@rtems.org>
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2007-01-10 Ralf Corsépius <ralf.corsepius@rtems.org>
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* config/bfin/t-bfin, config/bfin/t-bfin-elf: Remove GCC_CFLAGS.
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@ -20758,7 +20767,7 @@
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* config/frv/predicates.md (reg_or_0_operand): Accept
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CONST_DOUBLEs.
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2007-01-08 Ralf Corsépius <ralf.corsepius@rtems.org>
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2007-01-08 Ralf Corsépius <ralf.corsepius@rtems.org>
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* config/bfin/rtems.h, config/bfin/t-rtems: New.
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* config.gcc: Add bfin*-rtems*.
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@ -289,8 +289,9 @@ struct processor_costs {
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const int dmul; /* cost of DFmode multiplication (and fmadd). */
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const int sdiv; /* cost of SFmode division (fdivs). */
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const int ddiv; /* cost of DFmode division (fdiv). */
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const int cache_line_size; /* cache block in bytes. */
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const int l1_cache_lines; /* number of lines in L1 cache. */
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const int cache_line_size; /* cache line size in bytes. */
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const int l1_cache_size; /* size of l1 cache, in kilobytes. */
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const int l2_cache_size; /* size of l2 cache, in kilobytes. */
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const int simultaneous_prefetches; /* number of parallel prefetch
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operations. */
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};
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@ -315,6 +316,7 @@ struct processor_costs size32_cost = {
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32,
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0,
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0,
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0,
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};
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/* Instruction size costs on 64bit processors. */
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@ -333,6 +335,7 @@ struct processor_costs size64_cost = {
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128,
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0,
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0,
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0,
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};
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/* Instruction costs on RIOS1 processors. */
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@ -348,8 +351,9 @@ struct processor_costs rios1_cost = {
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COSTS_N_INSNS (2), /* dmul */
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COSTS_N_INSNS (19), /* sdiv */
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COSTS_N_INSNS (19), /* ddiv */
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32,
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1024, /* cache lines */
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128,
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64, /* l1 cache */
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512, /* l2 cache */
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0, /* streams */
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};
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@ -366,8 +370,9 @@ struct processor_costs rios2_cost = {
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COSTS_N_INSNS (2), /* dmul */
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COSTS_N_INSNS (17), /* sdiv */
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COSTS_N_INSNS (17), /* ddiv */
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32,
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1024, /* cache lines */
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256,
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256, /* l1 cache */
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1024, /* l2 cache */
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0, /* streams */
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};
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@ -385,7 +390,8 @@ struct processor_costs rs64a_cost = {
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COSTS_N_INSNS (31), /* sdiv */
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COSTS_N_INSNS (31), /* ddiv */
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128,
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1024, /* cache lines */
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128, /* l1 cache */
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2048, /* l2 cache */
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1, /* streams */
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};
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@ -402,8 +408,9 @@ struct processor_costs mpccore_cost = {
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COSTS_N_INSNS (5), /* dmul */
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COSTS_N_INSNS (10), /* sdiv */
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COSTS_N_INSNS (17), /* ddiv */
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128,
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512, /* cache lines */
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32,
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4, /* l1 cache */
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16, /* l2 cache */
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1, /* streams */
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};
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@ -421,7 +428,8 @@ struct processor_costs ppc403_cost = {
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COSTS_N_INSNS (11), /* sdiv */
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COSTS_N_INSNS (11), /* ddiv */
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32,
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128, /* cache lines */
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4, /* l1 cache */
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16, /* l2 cache */
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1, /* streams */
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};
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@ -439,7 +447,8 @@ struct processor_costs ppc405_cost = {
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COSTS_N_INSNS (11), /* sdiv */
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COSTS_N_INSNS (11), /* ddiv */
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32,
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512, /* cache lines */
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16, /* l1 cache */
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128, /* l2 cache */
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1, /* streams */
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};
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@ -457,7 +466,8 @@ struct processor_costs ppc440_cost = {
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COSTS_N_INSNS (19), /* sdiv */
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COSTS_N_INSNS (33), /* ddiv */
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32,
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1024, /* cache lines */
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32, /* l1 cache */
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256, /* l2 cache */
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1, /* streams */
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};
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@ -475,7 +485,8 @@ struct processor_costs ppc601_cost = {
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COSTS_N_INSNS (17), /* sdiv */
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COSTS_N_INSNS (31), /* ddiv */
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32,
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1024, /* cache lines */
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32, /* l1 cache */
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256, /* l2 cache */
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1, /* streams */
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};
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@ -493,7 +504,8 @@ struct processor_costs ppc603_cost = {
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COSTS_N_INSNS (18), /* sdiv */
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COSTS_N_INSNS (33), /* ddiv */
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32,
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256, /* cache lines */
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8, /* l1 cache */
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64, /* l2 cache */
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1, /* streams */
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};
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@ -511,7 +523,8 @@ struct processor_costs ppc604_cost = {
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COSTS_N_INSNS (18), /* sdiv */
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COSTS_N_INSNS (32), /* ddiv */
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32,
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512, /* cache lines */
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16, /* l1 cache */
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512, /* l2 cache */
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1, /* streams */
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};
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@ -529,7 +542,8 @@ struct processor_costs ppc604e_cost = {
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COSTS_N_INSNS (18), /* sdiv */
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COSTS_N_INSNS (32), /* ddiv */
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32,
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1024, /* cache lines */
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32, /* l1 cache */
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1024, /* l2 cache */
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1, /* streams */
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};
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@ -547,7 +561,8 @@ struct processor_costs ppc620_cost = {
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COSTS_N_INSNS (18), /* sdiv */
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COSTS_N_INSNS (32), /* ddiv */
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128,
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512, /* cache lines */
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32, /* l1 cache */
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1024, /* l2 cache */
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1, /* streams */
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};
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@ -565,7 +580,8 @@ struct processor_costs ppc630_cost = {
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COSTS_N_INSNS (17), /* sdiv */
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COSTS_N_INSNS (21), /* ddiv */
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128,
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512, /* cache lines */
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64, /* l1 cache */
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1024, /* l2 cache */
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1, /* streams */
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};
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@ -584,8 +600,9 @@ struct processor_costs ppccell_cost = {
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COSTS_N_INSNS (74/2), /* sdiv */
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COSTS_N_INSNS (74/2), /* ddiv */
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128,
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256, /* cache lines */
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6, /* streams */
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32, /* l1 cache */
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512, /* l2 cache */
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6, /* streams */
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};
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/* Instruction costs on PPC750 and PPC7400 processors. */
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@ -602,7 +619,8 @@ struct processor_costs ppc750_cost = {
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COSTS_N_INSNS (17), /* sdiv */
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COSTS_N_INSNS (31), /* ddiv */
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32,
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1024, /* cache lines */
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32, /* l1 cache */
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512, /* l2 cache */
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1, /* streams */
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};
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@ -620,7 +638,8 @@ struct processor_costs ppc7450_cost = {
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COSTS_N_INSNS (21), /* sdiv */
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COSTS_N_INSNS (35), /* ddiv */
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32,
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1024, /* cache lines */
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32, /* l1 cache */
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1024, /* l2 cache */
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1, /* streams */
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};
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@ -638,7 +657,8 @@ struct processor_costs ppc8540_cost = {
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COSTS_N_INSNS (29), /* sdiv */
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COSTS_N_INSNS (29), /* ddiv */
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32,
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1024, /* cache lines */
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32, /* l1 cache */
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256, /* l2 cache */
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1, /* prefetch streams /*/
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};
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@ -656,7 +676,8 @@ struct processor_costs power4_cost = {
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COSTS_N_INSNS (17), /* sdiv */
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COSTS_N_INSNS (17), /* ddiv */
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128,
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256, /* cache lines */
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32, /* l1 cache */
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1024, /* l2 cache */
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8, /* prefetch streams /*/
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};
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@ -674,7 +695,8 @@ struct processor_costs power6_cost = {
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COSTS_N_INSNS (13), /* sdiv */
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COSTS_N_INSNS (16), /* ddiv */
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128,
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512, /* cache lines */
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64, /* l1 cache */
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2048, /* l2 cache */
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16, /* prefetch streams */
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};
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@ -1799,9 +1821,11 @@ rs6000_override_options (const char *default_cpu)
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set_param_value ("simultaneous-prefetches",
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rs6000_cost->simultaneous_prefetches);
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if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
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set_param_value ("l1-cache-size", rs6000_cost->l1_cache_lines);
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set_param_value ("l1-cache-size", rs6000_cost->l1_cache_size);
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if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
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set_param_value ("l1-cache-line-size", rs6000_cost->cache_line_size);
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if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
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set_param_value ("l2-cache-size", rs6000_cost->l2_cache_size);
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}
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/* Implement targetm.vectorize.builtin_mask_for_load. */
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