rs6000.c (altivec_expand_vec_perm_le): Generalize for vector types other than V16QImode.
gcc: 2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * config/rs6000/rs6000.c (altivec_expand_vec_perm_le): Generalize for vector types other than V16QImode. * config/rs6000/altivec.md (altivec_vperm_<mode>): Change to a define_expand, and call altivec_expand_vec_perm_le when producing code with little endian element order. (*altivec_vperm_<mode>_internal): New insn having previous behavior of altivec_vperm_<mode>. (altivec_vperm_<mode>_uns): Change to a define_expand, and call altivec_expand_vec_perm_le when producing code with little endian element order. (*altivec_vperm_<mode>_uns_internal): New insn having previous behavior of altivec_vperm_<mode>_uns. gcc/testsuite: 2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com> * gcc.dg/vmx/3b-15.c: Remove special handling for little endian. * gcc.dg/vmx/perm.c: New. * gcc.dg/vmx/perm-be-order.c: New. From-SVN: r207415
This commit is contained in:
Bill Schmidt
William Schmidt
parent
b80afde960
commit
60331d000d
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@ -1,3 +1,18 @@
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2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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* config/rs6000/rs6000.c (altivec_expand_vec_perm_le): Generalize
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for vector types other than V16QImode.
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* config/rs6000/altivec.md (altivec_vperm_<mode>): Change to a
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define_expand, and call altivec_expand_vec_perm_le when producing
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code with little endian element order.
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(*altivec_vperm_<mode>_internal): New insn having previous
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behavior of altivec_vperm_<mode>.
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(altivec_vperm_<mode>_uns): Change to a define_expand, and call
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altivec_expand_vec_perm_le when producing code with little endian
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element order.
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(*altivec_vperm_<mode>_uns_internal): New insn having previous
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behavior of altivec_vperm_<mode>_uns.
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2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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* config/rs6000/altivec.md (UNSPEC_VSUMSWS_DIRECT): New unspec.
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@ -1826,7 +1826,22 @@
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"vrfiz %0,%1"
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[(set_attr "type" "vecfloat")])
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(define_insn "altivec_vperm_<mode>"
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(define_expand "altivec_vperm_<mode>"
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[(set (match_operand:VM 0 "register_operand" "=v")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v")
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(match_operand:VM 2 "register_operand" "v")
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(match_operand:V16QI 3 "register_operand" "v")]
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UNSPEC_VPERM))]
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"TARGET_ALTIVEC"
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{
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if (!VECTOR_ELT_ORDER_BIG)
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{
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altivec_expand_vec_perm_le (operands);
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DONE;
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}
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})
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(define_insn "*altivec_vperm_<mode>_internal"
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[(set (match_operand:VM 0 "register_operand" "=v")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v")
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(match_operand:VM 2 "register_operand" "v")
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@ -1836,7 +1851,22 @@
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"vperm %0,%1,%2,%3"
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[(set_attr "type" "vecperm")])
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(define_insn "altivec_vperm_<mode>_uns"
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(define_expand "altivec_vperm_<mode>_uns"
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[(set (match_operand:VM 0 "register_operand" "=v")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v")
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(match_operand:VM 2 "register_operand" "v")
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(match_operand:V16QI 3 "register_operand" "v")]
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UNSPEC_VPERM_UNS))]
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"TARGET_ALTIVEC"
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{
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if (!VECTOR_ELT_ORDER_BIG)
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{
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altivec_expand_vec_perm_le (operands);
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DONE;
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}
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})
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(define_insn "*altivec_vperm_<mode>_uns_internal"
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[(set (match_operand:VM 0 "register_operand" "=v")
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(unspec:VM [(match_operand:VM 1 "register_operand" "v")
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(match_operand:VM 2 "register_operand" "v")
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@ -29840,16 +29840,18 @@ altivec_expand_vec_perm_le (rtx operands[4])
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rtx op1 = operands[2];
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rtx sel = operands[3];
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rtx tmp = target;
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rtx splatreg = gen_reg_rtx (V16QImode);
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enum machine_mode mode = GET_MODE (target);
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/* Get everything in regs so the pattern matches. */
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if (!REG_P (op0))
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op0 = force_reg (V16QImode, op0);
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op0 = force_reg (mode, op0);
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if (!REG_P (op1))
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op1 = force_reg (V16QImode, op1);
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op1 = force_reg (mode, op1);
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if (!REG_P (sel))
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sel = force_reg (V16QImode, sel);
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if (!REG_P (target))
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tmp = gen_reg_rtx (V16QImode);
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tmp = gen_reg_rtx (mode);
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/* SEL = splat(31) - SEL. */
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/* We want to subtract from 31, but we can't vspltisb 31 since
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@ -29857,13 +29859,12 @@ altivec_expand_vec_perm_le (rtx operands[4])
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five bits of the permute control vector elements are used. */
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splat = gen_rtx_VEC_DUPLICATE (V16QImode,
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gen_rtx_CONST_INT (QImode, -1));
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emit_move_insn (tmp, splat);
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sel = gen_rtx_MINUS (V16QImode, tmp, sel);
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emit_move_insn (tmp, sel);
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emit_move_insn (splatreg, splat);
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sel = gen_rtx_MINUS (V16QImode, splatreg, sel);
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emit_move_insn (splatreg, sel);
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/* Permute with operands reversed and adjusted selector. */
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unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, tmp),
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UNSPEC_VPERM);
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unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, splatreg), UNSPEC_VPERM);
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/* Copy into target, possibly by way of a register. */
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if (!REG_P (target))
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@ -1,3 +1,9 @@
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2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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* gcc.dg/vmx/3b-15.c: Remove special handling for little endian.
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* gcc.dg/vmx/perm.c: New.
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* gcc.dg/vmx/perm-be-order.c: New.
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2014-02-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
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* gcc.dg/vmx/vsums.c: New.
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@ -3,11 +3,7 @@
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vector unsigned char
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f (vector unsigned char a, vector unsigned char b, vector unsigned char c)
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{
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#ifdef __BIG_ENDIAN__
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return vec_perm(a,b,c);
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#else
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return vec_perm(b,a,c);
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#endif
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}
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static void test()
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@ -16,13 +12,8 @@ static void test()
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8,9,10,11,12,13,14,15}),
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((vector unsigned char){70,71,72,73,74,75,76,77,
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78,79,80,81,82,83,84,85}),
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#ifdef __BIG_ENDIAN__
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((vector unsigned char){0x1,0x14,0x18,0x10,0x16,0x15,0x19,0x1a,
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0x1c,0x1c,0x1c,0x12,0x8,0x1d,0x1b,0xe})),
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#else
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((vector unsigned char){0x1e,0xb,0x7,0xf,0x9,0xa,0x6,0x5,
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0x3,0x3,0x3,0xd,0x17,0x2,0x4,0x11})),
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#endif
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((vector unsigned char){1,74,78,70,76,75,79,80,82,82,82,72,8,83,81,14})),
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"f");
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}
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@ -0,0 +1,74 @@
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/* { dg-options "-maltivec=be -mabi=altivec -std=gnu99 -mno-vsx" } */
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#include "harness.h"
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static void test()
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{
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/* Input vectors. */
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vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
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vector unsigned char vucb = {16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};
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vector signed char vsca = {-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1};
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vector signed char vscb = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
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vector unsigned short vusa = {0,1,2,3,4,5,6,7};
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vector unsigned short vusb = {8,9,10,11,12,13,14,15};
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vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};
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vector signed short vssb = {0,1,2,3,4,5,6,7};
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vector unsigned int vuia = {0,1,2,3};
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vector unsigned int vuib = {4,5,6,7};
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vector signed int vsia = {-4,-3,-2,-1};
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vector signed int vsib = {0,1,2,3};
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vector float vfa = {-4.0,-3.0,-2.0,-1.0};
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vector float vfb = {0.0,1.0,2.0,3.0};
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#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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vector unsigned char vucp = {15,16,14,17,13,18,12,19,11,20,10,21,9,22,8,23};
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vector unsigned char vscp = {15,16,14,17,13,18,12,19,11,20,10,21,9,22,8,23};
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vector unsigned char vusp = {15,14,17,16,13,12,19,18,11,10,21,20,9,8,23,22};
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vector unsigned char vssp = {15,14,17,16,13,12,19,18,11,10,21,20,9,8,23,22};
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vector unsigned char vuip = {15,14,13,12,19,18,17,16,11,10,9,8,23,22,21,20};
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vector unsigned char vsip = {15,14,13,12,19,18,17,16,11,10,9,8,23,22,21,20};
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vector unsigned char vfp = {15,14,13,12,19,18,17,16,11,10,9,8,23,22,21,20};
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#else
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vector unsigned char vucp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};
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vector unsigned char vscp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};
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vector unsigned char vusp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};
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vector unsigned char vssp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};
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vector unsigned char vuip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};
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vector unsigned char vsip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};
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vector unsigned char vfp = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};
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#endif
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/* Result vectors. */
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vector unsigned char vuc;
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vector signed char vsc;
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vector unsigned short vus;
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vector signed short vss;
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vector unsigned int vui;
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vector signed int vsi;
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vector float vf;
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/* Expected result vectors. */
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vector unsigned char vucr = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};
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vector signed char vscr = {-16,15,-15,14,-14,13,-13,12,-12,11,-11,10,-10,9,-9,8};
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vector unsigned short vusr = {0,15,1,14,2,13,3,12};
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vector signed short vssr = {-8,7,-7,6,-6,5,-5,4};
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vector unsigned int vuir = {0,7,1,6};
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vector signed int vsir = {-4,3,-3,2};
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vector float vfr = {-4.0,3.0,-3.0,2.0};
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vuc = vec_perm (vuca, vucb, vucp);
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vsc = vec_perm (vsca, vscb, vscp);
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vus = vec_perm (vusa, vusb, vusp);
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vss = vec_perm (vssa, vssb, vssp);
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vui = vec_perm (vuia, vuib, vuip);
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vsi = vec_perm (vsia, vsib, vsip);
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vf = vec_perm (vfa, vfb, vfp );
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check (vec_all_eq (vuc, vucr), "vuc");
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check (vec_all_eq (vsc, vscr), "vsc");
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check (vec_all_eq (vus, vusr), "vus");
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check (vec_all_eq (vss, vssr), "vss");
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check (vec_all_eq (vui, vuir), "vui");
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check (vec_all_eq (vsi, vsir), "vsi");
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check (vec_all_eq (vf, vfr), "vf" );
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}
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@ -0,0 +1,69 @@
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#include "harness.h"
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static void test()
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{
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/* Input vectors. */
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vector unsigned char vuca = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
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vector unsigned char vucb
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= {16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31};
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vector unsigned char vucp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};
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vector signed char vsca
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= {-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1};
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vector signed char vscb = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
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vector unsigned char vscp = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};
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vector unsigned short vusa = {0,1,2,3,4,5,6,7};
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vector unsigned short vusb = {8,9,10,11,12,13,14,15};
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vector unsigned char vusp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};
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vector signed short vssa = {-8,-7,-6,-5,-4,-3,-2,-1};
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vector signed short vssb = {0,1,2,3,4,5,6,7};
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vector unsigned char vssp = {0,1,30,31,2,3,28,29,4,5,26,27,6,7,24,25};
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vector unsigned int vuia = {0,1,2,3};
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vector unsigned int vuib = {4,5,6,7};
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vector unsigned char vuip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};
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vector signed int vsia = {-4,-3,-2,-1};
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vector signed int vsib = {0,1,2,3};
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vector unsigned char vsip = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};
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vector float vfa = {-4.0,-3.0,-2.0,-1.0};
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vector float vfb = {0.0,1.0,2.0,3.0};
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vector unsigned char vfp = {0,1,2,3,28,29,30,31,4,5,6,7,24,25,26,27};
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/* Result vectors. */
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vector unsigned char vuc;
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vector signed char vsc;
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vector unsigned short vus;
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vector signed short vss;
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vector unsigned int vui;
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vector signed int vsi;
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vector float vf;
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/* Expected result vectors. */
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vector unsigned char vucr = {0,31,1,30,2,29,3,28,4,27,5,26,6,25,7,24};
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vector signed char vscr = {-16,15,-15,14,-14,13,-13,12,-12,11,-11,10,-10,9,-9,8};
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vector unsigned short vusr = {0,15,1,14,2,13,3,12};
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vector signed short vssr = {-8,7,-7,6,-6,5,-5,4};
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vector unsigned int vuir = {0,7,1,6};
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vector signed int vsir = {-4,3,-3,2};
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vector float vfr = {-4.0,3.0,-3.0,2.0};
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vuc = vec_perm (vuca, vucb, vucp);
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vsc = vec_perm (vsca, vscb, vscp);
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vus = vec_perm (vusa, vusb, vusp);
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vss = vec_perm (vssa, vssb, vssp);
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vui = vec_perm (vuia, vuib, vuip);
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vsi = vec_perm (vsia, vsib, vsip);
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vf = vec_perm (vfa, vfb, vfp );
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check (vec_all_eq (vuc, vucr), "vuc");
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check (vec_all_eq (vsc, vscr), "vsc");
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check (vec_all_eq (vus, vusr), "vus");
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check (vec_all_eq (vss, vssr), "vss");
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check (vec_all_eq (vui, vuir), "vui");
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check (vec_all_eq (vsi, vsir), "vsi");
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check (vec_all_eq (vf, vfr), "vf" );
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}
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