aarch64: Use RTL builtins for FP ml[as]_n intrinsics
Rewrite floating-point vml[as][q]_n Neon intrinsics to use RTL builtins rather than inline assembly code, allowing for better scheduling and optimization. gcc/ChangeLog: 2021-01-18 Jonathan Wright <jonathan.wright@arm.com> * config/aarch64/aarch64-simd-builtins.def: Add float_ml[as]_n_builtin generator macros. * config/aarch64/aarch64-simd.md (*aarch64_mul3_elt_from_dup<mode>): Rename to... (mul_n<mode>3): This, and re-order arguments. (aarch64_float_mla_n<mode>): Define. (aarch64_float_mls_n<mode>): Define. * config/aarch64/arm_neon.h (vmla_n_f32): Use RTL builtin instead of inline asm. (vmlaq_n_f32): Likewise. (vmls_n_f32): Likewise. (vmlsq_n_f32): Likewise.
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Jonathan Wright
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f546e0d3d0
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60518e6473
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@ -668,6 +668,9 @@
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BUILTIN_VHSDF (TERNOP, fnma, 4, FP)
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VAR1 (TERNOP, fnma, 4, FP, hf)
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BUILTIN_VDQSF (TERNOP, float_mla_n, 0, FP)
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BUILTIN_VDQSF (TERNOP, float_mls_n, 0, FP)
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/* Implemented by aarch64_simd_bsl<mode>. */
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BUILTIN_VDQQH (BSL_P, simd_bsl, 0, NONE)
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VAR2 (BSL_P, simd_bsl,0, NONE, di, v2di)
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@ -750,14 +750,14 @@
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[(set_attr "type" "neon<fp>_mul_<Vetype>_scalar<q>")]
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)
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(define_insn "*aarch64_mul3_elt_from_dup<mode>"
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(define_insn "mul_n<mode>3"
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[(set (match_operand:VMUL 0 "register_operand" "=w")
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(mult:VMUL
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(vec_duplicate:VMUL
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(match_operand:<VEL> 1 "register_operand" "<h_con>"))
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(match_operand:VMUL 2 "register_operand" "w")))]
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(mult:VMUL
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(vec_duplicate:VMUL
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(match_operand:<VEL> 2 "register_operand" "<h_con>"))
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(match_operand:VMUL 1 "register_operand" "w")))]
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"TARGET_SIMD"
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"<f>mul\t%0.<Vtype>, %2.<Vtype>, %1.<Vetype>[0]";
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"<f>mul\t%0.<Vtype>, %1.<Vtype>, %2.<Vetype>[0]";
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[(set_attr "type" "neon<fp>_mul_<stype>_scalar<q>")]
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)
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@ -2636,6 +2636,40 @@
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[(set_attr "type" "neon_fp_abs_<stype><q>")]
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)
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(define_expand "aarch64_float_mla_n<mode>"
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[(set (match_operand:VDQSF 0 "register_operand")
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(plus:VDQSF
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(mult:VDQSF
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(vec_duplicate:VDQSF
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(match_operand:<VEL> 3 "register_operand"))
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(match_operand:VDQSF 2 "register_operand"))
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(match_operand:VDQSF 1 "register_operand")))]
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"TARGET_SIMD"
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{
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rtx scratch = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_mul_n<mode>3 (scratch, operands[2], operands[3]));
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emit_insn (gen_add<mode>3 (operands[0], operands[1], scratch));
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DONE;
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}
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)
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(define_expand "aarch64_float_mls_n<mode>"
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[(set (match_operand:VDQSF 0 "register_operand")
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(minus:VDQSF
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(match_operand:VDQSF 1 "register_operand")
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(mult:VDQSF
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(vec_duplicate:VDQSF
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(match_operand:<VEL> 3 "register_operand"))
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(match_operand:VDQSF 2 "register_operand"))))]
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"TARGET_SIMD"
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{
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rtx scratch = gen_reg_rtx (<MODE>mode);
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emit_insn (gen_mul_n<mode>3 (scratch, operands[2], operands[3]));
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emit_insn (gen_sub<mode>3 (operands[0], operands[1], scratch));
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DONE;
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}
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)
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(define_insn "fma<mode>4"
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[(set (match_operand:VHSDF 0 "register_operand" "=w")
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(fma:VHSDF (match_operand:VHSDF 1 "register_operand" "w")
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@ -7035,13 +7035,7 @@ __extension__ extern __inline float32x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmla_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
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{
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float32x2_t __result;
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float32x2_t __t1;
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__asm__ ("fmul %1.2s, %3.2s, %4.s[0]; fadd %0.2s, %0.2s, %1.2s"
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: "=w"(__result), "=w"(__t1)
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: "0"(__a), "w"(__b), "w"(__c)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_float_mla_nv2sf (__a, __b, __c);
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}
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__extension__ extern __inline int16x4_t
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@ -7388,13 +7382,7 @@ __extension__ extern __inline float32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmlaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
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{
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float32x4_t __result;
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float32x4_t __t1;
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__asm__ ("fmul %1.4s, %3.4s, %4.s[0]; fadd %0.4s, %0.4s, %1.4s"
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: "=w"(__result), "=w"(__t1)
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: "0"(__a), "w"(__b), "w"(__c)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_float_mla_nv4sf (__a, __b, __c);
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}
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__extension__ extern __inline int16x8_t
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@ -7481,13 +7469,7 @@ __extension__ extern __inline float32x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmls_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
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{
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float32x2_t __result;
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float32x2_t __t1;
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__asm__ ("fmul %1.2s, %3.2s, %4.s[0]; fsub %0.2s, %0.2s, %1.2s"
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: "=w"(__result), "=w"(__t1)
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: "0"(__a), "w"(__b), "w"(__c)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_float_mls_nv2sf (__a, __b, __c);
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}
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__extension__ extern __inline int16x4_t
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@ -7838,13 +7820,7 @@ __extension__ extern __inline float32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vmlsq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
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{
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float32x4_t __result;
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float32x4_t __t1;
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__asm__ ("fmul %1.4s, %3.4s, %4.s[0]; fsub %0.4s, %0.4s, %1.4s"
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: "=w"(__result), "=w"(__t1)
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: "0"(__a), "w"(__b), "w"(__c)
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: /* No clobbers */);
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return __result;
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return __builtin_aarch64_float_mls_nv4sf (__a, __b, __c);
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}
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__extension__ extern __inline int16x8_t
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