common.opt (fsched-pressure-algorithm=): New option.
gcc/ * common.opt (fsched-pressure-algorithm=): New option. * flag-types.h (sched_pressure_algorithm): New enum. * sched-int.h (sched_pressure_p): Replace with... (sched_pressure): ...this new variable. * haifa-sched.c (sched_pressure_p): Replace with... (sched_pressure): ...this new variable. (sched_regno_pressure_class, rank_for_schedule, ready_sort) (update_reg_and_insn_max_reg_pressure, schedule_insn) (debug_ready_list, prune_ready_list, schedule_block, sched_init) (sched_finish, fix_tick_ready, haifa_init_insn): Update accordingly. * sched-deps.c (init_insn_reg_pressure_info): Likewise. (sched_analyze_insn): Likewise. * sched-rgn.c (schedule_region): Likewise. * config/m68k/m68k.c (m68k_sched_variable_issue): Likewise. From-SVN: r186881
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
2b3ecd379c
commit
60867e8c63
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@ -1,3 +1,20 @@
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2012-04-26 Richard Sandiford <richard.sandiford@linaro.org>
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* common.opt (fsched-pressure-algorithm=): New option.
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* flag-types.h (sched_pressure_algorithm): New enum.
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* sched-int.h (sched_pressure_p): Replace with...
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(sched_pressure): ...this new variable.
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* haifa-sched.c (sched_pressure_p): Replace with...
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(sched_pressure): ...this new variable.
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(sched_regno_pressure_class, rank_for_schedule, ready_sort)
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(update_reg_and_insn_max_reg_pressure, schedule_insn)
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(debug_ready_list, prune_ready_list, schedule_block, sched_init)
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(sched_finish, fix_tick_ready, haifa_init_insn): Update accordingly.
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* sched-deps.c (init_insn_reg_pressure_info): Likewise.
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(sched_analyze_insn): Likewise.
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* sched-rgn.c (schedule_region): Likewise.
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* config/m68k/m68k.c (m68k_sched_variable_issue): Likewise.
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2012-04-26 Bernd Schmidt <bernds@codesourcery.com>
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* PR middle-end/52997
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@ -1665,6 +1665,19 @@ fsched-pressure
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Common Report Var(flag_sched_pressure) Init(0) Optimization
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Enable register pressure sensitive insn scheduling
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fsched-pressure-algorithm=
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Common Joined RejectNegative Enum(sched_pressure_algorithm) Var(flag_sched_pressure_algorithm) Init(SCHED_PRESSURE_WEIGHTED)
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-fsched-pressure-algorithm=[weighted|model] Set the pressure-scheduling algorithm
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Enum
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Name(sched_pressure_algorithm) Type(enum sched_pressure_algorithm) UnknownError(unknown %<fsched-pressure%> algorithm %qs)
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EnumValue
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Enum(sched_pressure_algorithm) String(weighted) Value(SCHED_PRESSURE_WEIGHTED)
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EnumValue
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Enum(sched_pressure_algorithm) String(model) Value(SCHED_PRESSURE_MODEL)
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fsched-spec
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Common Report Var(flag_schedule_speculative) Init(1) Optimization
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Allow speculative motion of non-loads
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@ -6090,7 +6090,7 @@ m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED,
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/* Scheduling for register pressure does not always take DFA into
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account. Workaround instruction buffer not being filled enough. */
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{
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gcc_assert (sched_pressure_p);
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gcc_assert (sched_pressure == SCHED_PRESSURE_WEIGHTED);
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insn_size = sched_ib.filled;
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}
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@ -106,6 +106,14 @@ enum symbol_visibility
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};
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#endif
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/* The algorithm used to implement -fsched-pressure. */
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enum sched_pressure_algorithm
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{
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SCHED_PRESSURE_NONE,
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SCHED_PRESSURE_WEIGHTED,
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SCHED_PRESSURE_MODEL
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};
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/* The algorithm used for the integrated register allocator (IRA). */
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enum ira_algorithm
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{
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@ -872,10 +872,10 @@ schedule_insns (void)
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/* Do register pressure sensitive insn scheduling if the flag is set
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up. */
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bool sched_pressure_p;
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enum sched_pressure_algorithm sched_pressure;
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/* Map regno -> its pressure class. The map defined only when
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SCHED_PRESSURE_P is true. */
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SCHED_PRESSURE is SCHED_PRESSURE_WEIGHTED. */
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enum reg_class *sched_regno_pressure_class;
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/* The current register pressure. Only elements corresponding pressure
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@ -1661,7 +1661,7 @@ rank_for_schedule (const void *x, const void *y)
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/* Make sure that priority of TMP and TMP2 are initialized. */
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gcc_assert (INSN_PRIORITY_KNOWN (tmp) && INSN_PRIORITY_KNOWN (tmp2));
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if (sched_pressure_p)
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if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
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{
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int diff;
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@ -1677,7 +1677,7 @@ rank_for_schedule (const void *x, const void *y)
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}
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if (sched_pressure_p
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if (sched_pressure == SCHED_PRESSURE_WEIGHTED
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&& (INSN_TICK (tmp2) > clock_var || INSN_TICK (tmp) > clock_var))
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{
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if (INSN_TICK (tmp) <= clock_var)
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@ -1995,7 +1995,7 @@ ready_sort (struct ready_list *ready)
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int i;
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rtx *first = ready_lastpos (ready);
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if (sched_pressure_p)
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if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
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{
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for (i = 0; i < ready->n_ready; i++)
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if (!DEBUG_INSN_P (first[i]))
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@ -2138,7 +2138,7 @@ update_reg_and_insn_max_reg_pressure (rtx insn)
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void
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sched_setup_bb_reg_pressure_info (basic_block bb, rtx after)
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{
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gcc_assert (sched_pressure_p);
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gcc_assert (sched_pressure == SCHED_PRESSURE_WEIGHTED);
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initiate_bb_reg_pressure_info (bb);
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setup_insn_max_reg_pressure (after, false);
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}
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@ -2243,7 +2243,7 @@ schedule_insn (rtx insn)
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fputc ('\n', sched_dump);
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}
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if (sched_pressure_p && !DEBUG_INSN_P (insn))
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if (sched_pressure == SCHED_PRESSURE_WEIGHTED && !DEBUG_INSN_P (insn))
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update_reg_and_insn_max_reg_pressure (insn);
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/* Scheduling instruction should have all its dependencies resolved and
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@ -3366,12 +3366,12 @@ debug_ready_list (struct ready_list *ready)
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fprintf (sched_dump, " %s:%d",
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(*current_sched_info->print_insn) (p[i], 0),
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INSN_LUID (p[i]));
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if (sched_pressure_p)
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if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
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fprintf (sched_dump, "(cost=%d",
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INSN_REG_PRESSURE_EXCESS_COST_CHANGE (p[i]));
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if (INSN_TICK (p[i]) > clock_var)
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fprintf (sched_dump, ":delay=%d", INSN_TICK (p[i]) - clock_var);
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if (sched_pressure_p)
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if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
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fprintf (sched_dump, ")");
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}
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fprintf (sched_dump, "\n");
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@ -4001,7 +4001,7 @@ prune_ready_list (state_t temp_state, bool first_cycle_insn_p,
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cost = 1;
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reason = "asm";
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}
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else if (sched_pressure_p)
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else if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
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cost = 0;
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else
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{
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@ -4377,7 +4377,7 @@ schedule_block (basic_block *target_bb)
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fprintf (sched_dump, ";;\tReady list (t = %3d): ",
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clock_var);
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debug_ready_list (&ready);
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if (sched_pressure_p)
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if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
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print_curr_reg_pressure ();
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}
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@ -4420,7 +4420,8 @@ schedule_block (basic_block *target_bb)
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else
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insn = ready_remove_first (&ready);
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if (sched_pressure_p && INSN_TICK (insn) > clock_var)
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if (sched_pressure == SCHED_PRESSURE_WEIGHTED
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&& INSN_TICK (insn) > clock_var)
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{
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ready_add (&ready, insn, true);
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advance = 1;
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@ -4497,7 +4498,7 @@ schedule_block (basic_block *target_bb)
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{
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memcpy (temp_state, curr_state, dfa_state_size);
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cost = state_transition (curr_state, insn);
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if (!sched_pressure_p)
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if (sched_pressure != SCHED_PRESSURE_WEIGHTED)
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gcc_assert (cost < 0);
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if (memcmp (temp_state, curr_state, dfa_state_size) != 0)
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cycle_issued_insns++;
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@ -4785,10 +4786,14 @@ sched_init (void)
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if (targetm.sched.dispatch (NULL_RTX, IS_DISPATCH_ON))
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targetm.sched.dispatch_do (NULL_RTX, DISPATCH_INIT);
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sched_pressure_p = (flag_sched_pressure && ! reload_completed
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&& common_sched_info->sched_pass_id == SCHED_RGN_PASS);
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if (flag_sched_pressure
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&& !reload_completed
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&& common_sched_info->sched_pass_id == SCHED_RGN_PASS)
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sched_pressure = flag_sched_pressure_algorithm;
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else
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sched_pressure = SCHED_PRESSURE_NONE;
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if (sched_pressure_p)
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if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
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ira_setup_eliminable_regset ();
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/* Initialize SPEC_INFO. */
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@ -4866,7 +4871,7 @@ sched_init (void)
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if (targetm.sched.init_global)
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targetm.sched.init_global (sched_dump, sched_verbose, get_max_uid () + 1);
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if (sched_pressure_p)
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if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
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{
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int i, max_regno = max_reg_num ();
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@ -4983,7 +4988,7 @@ void
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sched_finish (void)
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{
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haifa_finish_h_i_d ();
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if (sched_pressure_p)
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if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
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{
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if (regstat_n_sets_and_refs != NULL)
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regstat_free_n_sets_and_refs ();
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@ -5262,7 +5267,7 @@ fix_tick_ready (rtx next)
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INSN_TICK (next) = tick;
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delay = tick - clock_var;
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if (delay <= 0 || sched_pressure_p)
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if (delay <= 0 || sched_pressure == SCHED_PRESSURE_WEIGHTED)
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delay = QUEUE_READY;
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change_queue_index (next, delay);
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@ -6688,7 +6693,7 @@ haifa_init_insn (rtx insn)
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/* Extend dependency caches by one element. */
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extend_dependency_caches (1, false);
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}
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if (sched_pressure_p)
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if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
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init_insn_reg_pressure_info (insn);
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}
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@ -2168,7 +2168,7 @@ init_insn_reg_pressure_info (rtx insn)
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static struct reg_pressure_data *pressure_info;
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rtx link;
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gcc_assert (sched_pressure_p);
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gcc_assert (sched_pressure == SCHED_PRESSURE_WEIGHTED);
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if (! INSN_P (insn))
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return;
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@ -2951,7 +2951,7 @@ sched_analyze_insn (struct deps_desc *deps, rtx x, rtx insn)
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|| (NONJUMP_INSN_P (insn) && control_flow_insn_p (insn)))
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reg_pending_barrier = MOVE_BARRIER;
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if (sched_pressure_p)
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if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
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{
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setup_insn_reg_uses (deps, insn);
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init_insn_reg_pressure_info (insn);
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@ -649,7 +649,7 @@ extern struct haifa_sched_info *current_sched_info;
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/* Do register pressure sensitive insn scheduling if the flag is set
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up. */
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extern bool sched_pressure_p;
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extern enum sched_pressure_algorithm sched_pressure;
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/* Map regno -> its pressure class. The map defined only when
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SCHED_PRESSURE_P is true. */
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@ -2921,7 +2921,7 @@ schedule_region (int rgn)
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sched_extend_ready_list (rgn_n_insns);
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if (sched_pressure_p)
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if (sched_pressure == SCHED_PRESSURE_WEIGHTED)
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{
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sched_init_region_reg_pressure_info ();
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for (bb = 0; bb < current_nr_blocks; bb++)
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