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Add cpp support for ARM920 and ARM920T processor types. 

Minor formatting tidies in arm.c and arm.md

From-SVN: r27657
This commit is contained in:
Nick Clifton 1999-06-21 07:25:35 +00:00 committed by Nick Clifton
parent d4308a83ff
commit 60d0536b1e
4 changed files with 17 additions and 8 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
Mon Jun 21 14:58:42 1999 Nick Clifton <nickc@cygnus.com>
* config/arm/arm.h: Add cpp support for ARM920 and ARM920T cpu
types.
Mon Jun 21 06:22:21 1999 Mark Elbrecht <snowball3@bigfoot.com>
* i386/djgpp.h (LIB_SPEC): New.

2
gcc/config/arm/arm.c
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@ -73,7 +73,7 @@ static int const_ok_for_op RTX_CODE_PROTO ((Hint, Rcode));
/* True if we are currently building a constant table. */
int making_const_table;
/* Define the information needed to generate branch insns. This is
/* Define the information needed to generate branch insns. This is
stored from the compare operation. */
rtx arm_compare_op0, arm_compare_op1;

6
gcc/config/arm/arm.h
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@ -141,6 +141,8 @@ Unrecognized value in TARGET_CPU_DEFAULT.
%{march=arm8:-D__ARM_ARCH_4__} \
%{march=arm810:-D__ARM_ARCH_4__} \
%{march=arm9:-D__ARM_ARCH_4T__} \
%{march=arm920:-D__ARM_ARCH_4__} \
%{march=arm920t:-D__ARM_ARCH_4T__} \
%{march=arm9tdmi:-D__ARM_ARCH_4T__} \
%{march=strongarm:-D__ARM_ARCH_4__} \
%{march=strongarm110:-D__ARM_ARCH_4__} \
@ -171,6 +173,8 @@ Unrecognized value in TARGET_CPU_DEFAULT.
%{mcpu=arm8:-D__ARM_ARCH_4__} \
%{mcpu=arm810:-D__ARM_ARCH_4__} \
%{mcpu=arm9:-D__ARM_ARCH_4T__} \
%{mcpu=arm920:-D__ARM_ARCH_4__} \
%{mcpu=arm920t:-D__ARM_ARCH_4T__} \
%{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
%{mcpu=strongarm:-D__ARM_ARCH_4__} \
%{mcpu=strongarm110:-D__ARM_ARCH_4__} \
@ -317,7 +321,7 @@ function tries to return. */
#define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
#define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
/* Note: TARGET_SHORT_BY_BYTES is really a misnomer. What it means is
that short values sould not be accessed using word load instructions
that short values should not be accessed using word load instructions
as there is a possibility that they may not be word aligned and this
would generate an MMU fault. On processors which do not have a 16 bit
load instruction therefore, short values must be loaded by individual

12
gcc/config/arm/arm.md
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@ -4267,7 +4267,7 @@
;; Often the return insn will be the same as loading from memory, so set attr
(define_insn "return"
[(return)]
"USE_RETURN_INSN(FALSE)"
"USE_RETURN_INSN (FALSE)"
"*
{
extern int arm_ccfsm_state;
@ -4287,7 +4287,7 @@
[(match_operand 1 "cc_register" "") (const_int 0)])
(return)
(pc)))]
"USE_RETURN_INSN(TRUE)"
"USE_RETURN_INSN (TRUE)"
"*
{
extern int arm_ccfsm_state;
@ -4308,7 +4308,7 @@
[(match_operand 1 "cc_register" "") (const_int 0)])
(pc)
(return)))]
"USE_RETURN_INSN(TRUE)"
"USE_RETURN_INSN (TRUE)"
"*
{
extern int arm_ccfsm_state;
@ -5974,7 +5974,7 @@
(match_operand:SI 1 "general_operand" "g"))
(clobber (reg:SI 14))])
(return)]
"(GET_CODE (operands[0]) == SYMBOL_REF && USE_RETURN_INSN(FALSE)
"(GET_CODE (operands[0]) == SYMBOL_REF && USE_RETURN_INSN (FALSE)
&& !get_frame_size () && !current_function_calls_alloca
&& !frame_pointer_needed && !current_function_args_size)"
"*
@ -6002,7 +6002,7 @@
(match_operand:SI 2 "general_operand" "g")))
(clobber (reg:SI 14))])
(return)]
"(GET_CODE (operands[1]) == SYMBOL_REF && USE_RETURN_INSN(FALSE)
"(GET_CODE (operands[1]) == SYMBOL_REF && USE_RETURN_INSN (FALSE)
&& !get_frame_size () && !current_function_calls_alloca
&& !frame_pointer_needed && !current_function_args_size)"
"*
@ -6034,7 +6034,7 @@
(clobber (reg:SI 14))])
(use (match_dup 0))
(return)]
"(GET_CODE (operands[1]) == SYMBOL_REF && USE_RETURN_INSN(FALSE)
"(GET_CODE (operands[1]) == SYMBOL_REF && USE_RETURN_INSN (FALSE)
&& !get_frame_size () && !current_function_calls_alloca
&& !frame_pointer_needed && !current_function_args_size)"
"*