re PR target/28623 (ICE in extract_insn, at recog.c:2077 (nrecognizable insn) [alpha])
PR target/28623 * config/alpha/alpha.c (get_unaligned_address): Remove extra_offset argument; update all callers. (get_unaligned_offset): New. * config/alpha/alpha.md (extendqidi2, extendhidi2): Don't use get_unaligned_address, just pass on the address directly. (unaligned_extendqidi): Use gen_lowpart instead of open-coding the subreg in the helper patterns. (unaligned_extendqidi_le): Use get_unaligned_offset. (unaligned_extendqidi_be, unaligned_extendhidi_le): Likewise. (unaligned_extendhidi_be): Likewise. (unaligned_extendhidi): Tidy. * config/alpha/alpha-protos.h: Update. From-SVN: r124002
This commit is contained in:
parent
f326fd7a03
commit
60e9352519
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@ -1,3 +1,19 @@
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2007-04-20 Richard Henderson <rth@redhat.com>
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PR target/28623
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* config/alpha/alpha.c (get_unaligned_address): Remove extra_offset
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argument; update all callers.
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(get_unaligned_offset): New.
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* config/alpha/alpha.md (extendqidi2, extendhidi2): Don't use
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get_unaligned_address, just pass on the address directly.
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(unaligned_extendqidi): Use gen_lowpart instead of open-coding
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the subreg in the helper patterns.
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(unaligned_extendqidi_le): Use get_unaligned_offset.
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(unaligned_extendqidi_be, unaligned_extendhidi_le): Likewise.
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(unaligned_extendhidi_be): Likewise.
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(unaligned_extendhidi): Tidy.
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* config/alpha/alpha-protos.h: Update.
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2007-04-20 Richard Henderson <rth@redhat.com>
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2007-04-20 Richard Henderson <rth@redhat.com>
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* config/alpha/alpha.h (CPP_SPEC, CPP_SUBTARGET_SPEC): Remove.
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* config/alpha/alpha.h (CPP_SPEC, CPP_SUBTARGET_SPEC): Remove.
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@ -47,7 +47,8 @@ extern rtx alpha_legitimize_reload_address (rtx, enum machine_mode,
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extern rtx split_small_symbolic_operand (rtx);
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extern rtx split_small_symbolic_operand (rtx);
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extern void get_aligned_mem (rtx, rtx *, rtx *);
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extern void get_aligned_mem (rtx, rtx *, rtx *);
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extern rtx get_unaligned_address (rtx, int);
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extern rtx get_unaligned_address (rtx);
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extern rtx get_unaligned_offset (rtx, HOST_WIDE_INT);
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extern enum reg_class alpha_preferred_reload_class (rtx, enum reg_class);
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extern enum reg_class alpha_preferred_reload_class (rtx, enum reg_class);
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extern enum reg_class alpha_secondary_reload_class (enum reg_class,
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extern enum reg_class alpha_secondary_reload_class (enum reg_class,
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enum machine_mode, rtx,
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enum machine_mode, rtx,
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@ -1461,7 +1461,7 @@ get_aligned_mem (rtx ref, rtx *paligned_mem, rtx *pbitnum)
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Add EXTRA_OFFSET to the address we return. */
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Add EXTRA_OFFSET to the address we return. */
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rtx
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rtx
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get_unaligned_address (rtx ref, int extra_offset)
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get_unaligned_address (rtx ref)
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{
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{
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rtx base;
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rtx base;
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HOST_WIDE_INT offset = 0;
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HOST_WIDE_INT offset = 0;
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@ -1481,7 +1481,23 @@ get_unaligned_address (rtx ref, int extra_offset)
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if (GET_CODE (base) == PLUS)
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if (GET_CODE (base) == PLUS)
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offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
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offset += INTVAL (XEXP (base, 1)), base = XEXP (base, 0);
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return plus_constant (base, offset + extra_offset);
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return plus_constant (base, offset);
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}
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/* Compute a value X, such that X & 7 == (ADDR + OFS) & 7.
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X is always returned in a register. */
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rtx
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get_unaligned_offset (rtx addr, HOST_WIDE_INT ofs)
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{
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if (GET_CODE (addr) == PLUS)
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{
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ofs += INTVAL (XEXP (addr, 1));
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addr = XEXP (addr, 0);
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}
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return expand_simple_binop (Pmode, PLUS, addr, GEN_INT (ofs & 7),
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NULL_RTX, 1, OPTAB_LIB_WIDEN);
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}
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}
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/* On the Alpha, all (non-symbolic) constants except zero go into
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/* On the Alpha, all (non-symbolic) constants except zero go into
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@ -2230,7 +2246,7 @@ alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands)
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seq = ((mode == QImode
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seq = ((mode == QImode
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? gen_unaligned_loadqi
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? gen_unaligned_loadqi
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: gen_unaligned_loadhi)
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: gen_unaligned_loadhi)
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(subtarget, get_unaligned_address (operands[1], 0),
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(subtarget, get_unaligned_address (operands[1]),
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temp1, temp2));
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temp1, temp2));
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alpha_set_memflags (seq, operands[1]);
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alpha_set_memflags (seq, operands[1]);
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emit_insn (seq);
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emit_insn (seq);
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@ -2269,7 +2285,7 @@ alpha_expand_mov_nobwx (enum machine_mode mode, rtx *operands)
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rtx seq = ((mode == QImode
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rtx seq = ((mode == QImode
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? gen_unaligned_storeqi
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? gen_unaligned_storeqi
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: gen_unaligned_storehi)
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: gen_unaligned_storehi)
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(get_unaligned_address (operands[0], 0),
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(get_unaligned_address (operands[0]),
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operands[1], temp1, temp2, temp3));
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operands[1], temp1, temp2, temp3));
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alpha_set_memflags (seq, operands[0]);
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alpha_set_memflags (seq, operands[0]);
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@ -1664,10 +1664,7 @@
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if (unaligned_memory_operand (operands[1], QImode))
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if (unaligned_memory_operand (operands[1], QImode))
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{
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{
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rtx seq
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rtx seq = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0));
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= gen_unaligned_extendqidi (operands[0],
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get_unaligned_address (operands[1], 1));
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alpha_set_memflags (seq, operands[1]);
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alpha_set_memflags (seq, operands[1]);
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emit_insn (seq);
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emit_insn (seq);
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DONE;
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DONE;
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@ -1727,9 +1724,7 @@
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if (unaligned_memory_operand (operands[1], HImode))
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if (unaligned_memory_operand (operands[1], HImode))
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{
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{
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rtx seq
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rtx seq = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0));
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= gen_unaligned_extendhidi (operands[0],
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get_unaligned_address (operands[1], 2));
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alpha_set_memflags (seq, operands[1]);
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alpha_set_memflags (seq, operands[1]);
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emit_insn (seq);
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emit_insn (seq);
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@ -1744,12 +1739,13 @@
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;; as a pattern saves one instruction. The code is similar to that for
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;; as a pattern saves one instruction. The code is similar to that for
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;; the unaligned loads (see below).
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;; the unaligned loads (see below).
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;;
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;;
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;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
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;; Operand 1 is the address, operand 0 is the result.
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(define_expand "unaligned_extendqidi"
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(define_expand "unaligned_extendqidi"
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[(use (match_operand:QI 0 "register_operand" ""))
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[(use (match_operand:QI 0 "register_operand" ""))
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(use (match_operand:DI 1 "address_operand" ""))]
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(use (match_operand:DI 1 "address_operand" ""))]
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""
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""
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{
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{
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operands[0] = gen_lowpart (DImode, operands[0]);
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if (WORDS_BIG_ENDIAN)
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if (WORDS_BIG_ENDIAN)
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emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
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emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
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else
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else
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@ -1758,48 +1754,40 @@
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})
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})
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(define_expand "unaligned_extendqidi_le"
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(define_expand "unaligned_extendqidi_le"
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[(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
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[(set (match_dup 3)
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(set (match_dup 3)
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(mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
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(mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
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(const_int -8))))
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(set (match_dup 4)
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(set (match_dup 4)
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(ashift:DI (match_dup 3)
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(ashift:DI (match_dup 3)
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(minus:DI (const_int 64)
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(minus:DI (const_int 64)
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(ashift:DI
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(ashift:DI
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(and:DI (match_dup 2) (const_int 7))
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(and:DI (match_dup 2) (const_int 7))
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(const_int 3)))))
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(const_int 3)))))
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(set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
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(set (match_operand:DI 0 "register_operand" "")
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(ashiftrt:DI (match_dup 4) (const_int 56)))]
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(ashiftrt:DI (match_dup 4) (const_int 56)))]
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"! WORDS_BIG_ENDIAN"
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"! WORDS_BIG_ENDIAN"
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{
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{
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operands[2] = gen_reg_rtx (DImode);
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operands[2] = get_unaligned_offset (operands[1], 1);
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operands[3] = gen_reg_rtx (DImode);
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operands[3] = gen_reg_rtx (DImode);
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operands[4] = gen_reg_rtx (DImode);
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operands[4] = gen_reg_rtx (DImode);
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})
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})
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(define_expand "unaligned_extendqidi_be"
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(define_expand "unaligned_extendqidi_be"
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[(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
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[(set (match_dup 3)
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(set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
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(mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
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(set (match_dup 4)
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(set (match_dup 4)
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(mem:DI (and:DI (match_dup 3)
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(ashift:DI (match_dup 3)
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(const_int -8))))
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(set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
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(set (match_dup 6)
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(ashift:DI (match_dup 4)
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(ashift:DI
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(ashift:DI
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(and:DI
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(and:DI
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(plus:DI (match_dup 5) (const_int 1))
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(plus:DI (match_dup 2) (const_int 1))
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(const_int 7))
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(const_int 7))
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(const_int 3))))
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(const_int 3))))
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(set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
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(set (match_operand:DI 0 "register_operand" "")
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(ashiftrt:DI (match_dup 6) (const_int 56)))]
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(ashiftrt:DI (match_dup 4) (const_int 56)))]
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"WORDS_BIG_ENDIAN"
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"WORDS_BIG_ENDIAN"
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{
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{
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operands[2] = gen_reg_rtx (DImode);
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operands[2] = get_unaligned_offset (operands[1], -1);
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operands[3] = gen_reg_rtx (DImode);
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operands[3] = gen_reg_rtx (DImode);
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operands[4] = gen_reg_rtx (DImode);
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operands[4] = gen_reg_rtx (DImode);
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operands[5] = gen_reg_rtx (DImode);
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operands[6] = gen_reg_rtx (DImode);
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})
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})
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(define_expand "unaligned_extendhidi"
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(define_expand "unaligned_extendhidi"
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@ -1808,17 +1796,16 @@
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""
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""
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{
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{
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operands[0] = gen_lowpart (DImode, operands[0]);
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operands[0] = gen_lowpart (DImode, operands[0]);
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emit_insn ((WORDS_BIG_ENDIAN
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if (WORDS_BIG_ENDIAN)
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? gen_unaligned_extendhidi_be
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emit_insn (gen_unaligned_extendhidi_be (operands[0], operands[1]));
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: gen_unaligned_extendhidi_le) (operands[0], operands[1]));
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else
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emit_insn (gen_unaligned_extendhidi_le (operands[0], operands[1]));
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DONE;
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DONE;
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})
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})
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(define_expand "unaligned_extendhidi_le"
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(define_expand "unaligned_extendhidi_le"
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[(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
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[(set (match_dup 3)
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(set (match_dup 3)
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(mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
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(mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
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(const_int -8))))
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(set (match_dup 4)
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(set (match_dup 4)
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(ashift:DI (match_dup 3)
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(ashift:DI (match_dup 3)
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(minus:DI (const_int 64)
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(minus:DI (const_int 64)
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@ -1829,34 +1816,28 @@
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(ashiftrt:DI (match_dup 4) (const_int 48)))]
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(ashiftrt:DI (match_dup 4) (const_int 48)))]
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"! WORDS_BIG_ENDIAN"
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"! WORDS_BIG_ENDIAN"
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{
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{
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operands[2] = gen_reg_rtx (DImode);
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operands[2] = get_unaligned_offset (operands[1], 2);
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operands[3] = gen_reg_rtx (DImode);
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operands[3] = gen_reg_rtx (DImode);
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operands[4] = gen_reg_rtx (DImode);
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operands[4] = gen_reg_rtx (DImode);
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})
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})
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(define_expand "unaligned_extendhidi_be"
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(define_expand "unaligned_extendhidi_be"
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[(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
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[(set (match_dup 3)
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(set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
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(mem:DI (and:DI (match_operand:DI 1 "" "") (const_int -8))))
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(set (match_dup 4)
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(set (match_dup 4)
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(mem:DI (and:DI (match_dup 3)
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(ashift:DI (match_dup 3)
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(const_int -8))))
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(set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
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(set (match_dup 6)
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(ashift:DI (match_dup 4)
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(ashift:DI
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(ashift:DI
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(and:DI
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(and:DI
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(plus:DI (match_dup 5) (const_int 1))
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(plus:DI (match_dup 2) (const_int 1))
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(const_int 7))
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(const_int 7))
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(const_int 3))))
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(const_int 3))))
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(set (match_operand:DI 0 "register_operand" "")
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(set (match_operand:DI 0 "register_operand" "")
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(ashiftrt:DI (match_dup 6) (const_int 48)))]
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(ashiftrt:DI (match_dup 4) (const_int 48)))]
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"WORDS_BIG_ENDIAN"
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"WORDS_BIG_ENDIAN"
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{
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{
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operands[2] = gen_reg_rtx (DImode);
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operands[2] = get_unaligned_offset (operands[1], -1);
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operands[3] = gen_reg_rtx (DImode);
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operands[3] = gen_reg_rtx (DImode);
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operands[4] = gen_reg_rtx (DImode);
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operands[4] = gen_reg_rtx (DImode);
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operands[5] = gen_reg_rtx (DImode);
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operands[6] = gen_reg_rtx (DImode);
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})
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})
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(define_insn "*extxl_const"
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(define_insn "*extxl_const"
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@ -6133,7 +6114,7 @@
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else
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else
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scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
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scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
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addr = get_unaligned_address (operands[1], 0);
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addr = get_unaligned_address (operands[1]);
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operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
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operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
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seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]);
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seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]);
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alpha_set_memflags (seq, operands[1]);
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alpha_set_memflags (seq, operands[1]);
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@ -6167,7 +6148,7 @@
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else
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else
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scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
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scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
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addr = get_unaligned_address (operands[1], 0);
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addr = get_unaligned_address (operands[1]);
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operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
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operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
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seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]);
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seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]);
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alpha_set_memflags (seq, operands[1]);
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alpha_set_memflags (seq, operands[1]);
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@ -6191,7 +6172,7 @@
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}
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}
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else
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else
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{
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{
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rtx addr = get_unaligned_address (operands[0], 0);
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rtx addr = get_unaligned_address (operands[0]);
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rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
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rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
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rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
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rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
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rtx scratch3 = scratch1;
|
rtx scratch3 = scratch1;
|
||||||
|
@ -6223,7 +6204,7 @@
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
rtx addr = get_unaligned_address (operands[0], 0);
|
rtx addr = get_unaligned_address (operands[0]);
|
||||||
rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
|
rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
|
||||||
rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
|
rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
|
||||||
rtx scratch3 = scratch1;
|
rtx scratch3 = scratch1;
|
||||||
|
|
Loading…
Reference in New Issue